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Intel manual 2.6.3PCI Ids, 2.6.4Relationship between PCI IRQ and PCI Device, 6.STL2 PCI IDs

Models: STL2

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STL2 Server Board Architecture Overview

STL2 Server Board TPS

2.6.3PCI Ids

The STL2 server board PCI Ids are defined as follows:

Table 2-6. STL2 PCI IDs

	Device			Bus Number			Device Number			Slot ID Signal
				[23:16]			[15:11]
	NB6635 North Bridge 3.0LE			00h			00000b

	ATI* Rage IIC			00h			00010b			P32_AD18

	Intel 82559			00h			00011b			P32_AD19

	Adaptec* AIC-7899			00h			00100b			P32_AD20

	Slot 1 (32 bit)			00h			00110b			P32_AD22

	Slot 2 (32 bit)			00h			00111b			P32_AD23

	Slot 2 (32 bit)			00h			01000b			P32_AD24

	Slot 2 (32 bit)			00h			01001b			P32_AD25

	IB6566 South Bridge			00h			01111b			P32_AD31

	Slot 2 (32 bit)			00h			01010b			P32_AD26

	Slot 2 (32 bit)			00h			01011b			P32_AD27

Note:

Do not change the BUSNUM register (Offset 44h) in the NB6635 North Bridge 3.0LE from the default value.

2.6.4Relationship between PCI IRQ and PCI Device

The relationship between PCI IRQ and PCI devices are defined as follows on the STL2 server board:

	PCI IRQ			PCI Device
	PCI IRQ 0			Adaptec AIC-7899 SCSI Channel A

	PCI IRQ 1			Adaptec AIC-7899 SCSI Channel B

	PCI IRQ 2			Intel 82559

	PCI IRQ 3			ATI Rage IIC

	PCI IRQ 4			PCI Slot 2 (INTA)

	PCI IRQ 5			PCI Slot 3 (INTA)

	PCI IRQ 6			Not Used

	PCI IRQ 7			PCI Slot 4 (INTA)

	PCI IRQ 8			PCI Slot 5 (INTA)

	PCI IRQ 9			PCI Slot 6 (INTA)

	PCI IRQ 10			PCI Slot 1 (INTA)

	PCI IRQ 11			PCI Slot 1 (INTB), PCI Slot 2 (INTB), PCI Slot 3 (INTC), PCI Slot 4 (INTB), PCI Slot 5 (INTC), PCI
				Slot 6 (INTD)

	PCI IRQ 12			PCI Slot 1 (INTC), PCI Slot 2 (INTC), PCI Slot 3 (INTD), PCI Slot 4 (INTC), PCI Slot 5 (INTD), PCI
				Slot 6 (INTB)

	PCI IRQ 13			PCI Slot 1 (INTD), PCI Slot 2 (INTD), PCI Slot 3 (INTB), PCI Slot 4 (INTC), PCI Slot 5 (INTD), PCI
				Slot 6 (INTB)

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Intel manual 2.6.3PCI Ids, 2.6.4Relationship between PCI IRQ and PCI Device, 6.STL2 PCI IDs

Contents

Technical Product Specification Revision September 22, Enterprise Platforms GroupSTL2 Server Board Revision History DisclaimersRevision History STL2 Server Board TPSTable of Contents Introduction2. STL2 Server Board Architecture Overview Server Management4. Basic Input Output System BIOS 5. Jumpers and Connectors4-29 5-61Power Consumption Mechanical Specifications6-81 7-83List of Figures List of Tables Table 4-26.POST Error Messages and Codes 1.3STL2 Server Board Feature Overview 1.Introduction1.1Purpose 1.2Audience1.4STL2 Server Board Block Diagram STL2 Server Board Block Diagram Figure 1-1.STL2 Server Board Block DiagramServerSet 3.0 LE STL2 Features BIOSIntroduction < This page intentionally left blank >STL2 Server Board TPS 2.1 Intel Pentium III Processor Subsystem 2.STL2 Server Board Architecture Overview2.1.1Supported Processor Types 2.1.2Dual Processor Operation 2.1.3PGA370 Socket2.1.5Termination Package 2.1.6APIC Bus2.2ServerWorks ServerSet III LE Chipset 2.3Memory∙NB6635 North Bridge 3.0LE ∙IB6566 South Bridge2.4.164-bit /66 MHz PCI Subsystem 2.4PCI I/O Subsystem2.4.1.1Ultra160 / Ultra WideSCSI Controller 2.4.1.1.1AIC-7899Supported PCI Commands Revision2.4.1.1.2SCSI Bus 2.4.232-bit/33MHz PCI Subsystem2.4.2.1Network Interface Controller NIC 2.4.2.1.1Supported Network Features 2.4.2.2.1Video Controller PCI Signals 2.4.2.2Video Controller2.4.2.2.2Video Controller PCI Commands 2.4.2.2.3Video ModesTable 2-4.Video Controller Supported PCI Commands Table 2-5.Standard VGA Modes2.4.2.3.1PCI Interface 2.4.2.3IB6566 South Bridge2.4.2.3.2PCI Bus Master IDE Interface 2.4.2.6Power Management 2.5Chipset Support Components2.5.1Legacy I/O Super I/O National* PC97317VUL 2.4.2.3.3USB Interface2.5.1.4Keyboard and Mouse Connectors 2.5.1.7Power Management Controller2.5.1.1Serial Ports 2.5.1.2Parallel Port2.5.2BIOS Flash 2.5.3External Device Connectors2.6.1Default I/O APIC 2.6Interrupt Routing2-18 SouthInterrupt RouterRevision 2-192.6.4Relationship between PCI IRQ and PCI Device 2.6.3PCI IdsTable 2-6.STL2 PCI IDs Revision 2-21STL2 Server Board TPS STL2 Server Board Architecture OverviewPage 3.Server Management 3.1Baseboard Management Controller3.2Hardware Sensors ∙Monitors the event receiver∙Controls Wake-on-Lanvia Magic Packet* support 3-24Revision 3-253-26 Platform Security3.3ACPI 3.4AC Link Mode 3.5Wake On LAN Function4.Basic Input Output System BIOS 4.1BIOS Overview4.1.2Flash Update Utility 4.1.1System BIOS4.1.2.1System Flash ROM Layout 4.2.1Configuration Utilities Overview 4.2Setup Utility4.2.2Setup Utility Operation 4.2.2.1Entering Setup Utility 4.2.2.2Keyboard Command BarEnter Execute Command F1 HelpF9 Setup Defaults ←→ Select MenuF5/– Change Value F6/+ Change Value4.2.2.4Main Menu Selections ∙System Menu ∙Boot Menu ∙Exit MenuThese and associated submenus are described below Table 4-2.Main Menu SelectionsRevision Table 4-4.Processor Settings Submenu Selections4-35 Table 4-5.Advanced Menu Selections 4.2.2.5Advanced Menu Selections4-36 Revision 4-37Table 4-8.PCI Device Submenu Selections Table 4-9.Option ROM Submenu SelectionsTable 4-10.Numlock Submenu Selections 4-384.2.2.6Security Menu Selections Table 4-11.Security Menu SelectionsRevision 4-394.2.2.7System Hardware Menu Selections Table 4-12.Secure Mode Submenu SelectionsTable 4-13.Server Menu Selections Table 4-14.Wake On Events Submenu Selections4.2.2.8Boot Menu Selections Table 4-16.Boot Menu SelectionsTable 4-17.Boot Device Priority Selections Table 4-15.Console Redirection Submenu Selections4.3CMOS Memory Definition 4.2.2.9Exit Menu Selections4.5Flash Update Utility 4.4CMOS Default Override4.5.1Loading the System BIOS 4.5.2.1User-suppliedBIOS Code Support 4.5.2OEM CustomizationRevision 4-45# of bit available –1 Bit offset from start of CMOS of first bit4.5.2.2Scan Point Definitions Basic Input Output System BIOSSTL2 Server Board TPS Scan Point4.5.3Language Area 4.5.4Recovery Mode4.5.2.3OEM Splash Screen 4.6Error Messages and Error Codes 4.6.1POST CodesTable 4-24.Standard BIOS Port-80Codes ∙Each group is made one-based1 throughExample Checkpoint 04Bh will be broken down toConfigure advanced chipset registers 4-50Revision 4-514.6.2POST Error Codes and Messages Table 4-25.Recovery BIOS Port-80CodesTable 4-26.POST Error Messages and Codes 4-52Revision 4-53Basic Input Output System BIOS Error MessageError 4-544.7.1BIOS Revision Level Identification 4.7Identifying BIOS and BMC Revision Levels4.7.2BMC Revision Level Identification 4.8Adaptec SCSI Utility 4.8.2Adaptec SCSI Utility Configuration Settings4.8.1Running the SCSI Utility Basic Input Output System BIOS Recommended Setting orUser Setting Revision4.8.3Exiting Adaptec SCSI Utility 4-58Revision < This page intentionally left blank >4-59 Page 5.Jumpers and Connectors Jumper and connector location key for FigureRevision 5-61Figure 5-2.I/O Back Panel Connectors I/O Back Panel location key for Figure5-62 5.1Jumper Blocks 5.1.1.1Clearing and Changing a Password 5.1.1.2Clearing CMOSRevision 5.1.1.3Perfoming a BIOS Recovery Boot5-65 5.1.2Setting Configuration Jumper Block 1L4 5.2Connectors 5.1.3Setting Configuration Jumper Block 6A5.2.1Main ATX Power Connector P33 5.2.2Auxilary ATX Power Connector P345.2.3I2C Power Connector P37 Table 5-6.Main ATX Power Connector Pinout5.2.4System Fan Connectors P29, P27, P11 5.2.5Processor Connectors P12, P365.2.6Speaker Connector P31 5.2.7Speaker Connector P255.2.8Diskette Drive Connector P20 5.2.9SVGA Video PortFigure 5-3.Diskette Drive Connector Pin Diagram Table 5-13.Diskette Drive Connector Pinout5.2.10Keyboard and Mouse Connectors 5.2.11Parallel Port5.2.12Serial Ports COM1 and COM2 Table 5-15.Keyboard and Mouse Connector Pinouts5.2.13RJ-45LAN Connector 5.2.14USB ConnectorsTable 5-18. RJ-45LAN Connector Signals Table 5-19.USB Connectors5.2.15Ultra SCSI Connector P9 5.2.16Ultra160 SCSI Connector P8Table 5-20.Ultra SCSI Connector Pinout Table 5-21.Ultra160 SCSI Connector5.2.17IDE Connector P19 Figure 5-4.IDE Connector Pin DiagramTable 5-22.IDE Connector Pinout 5-745.2.1832-BitPCI Connector Table 5-23. 32-BitPCI Connector PinoutRevision 5-75Table 5-24. 64-BitPCI Connctor Pinout 5.2.1964-BitPCI Connector5-76 5.2.20Front Panel 24-pinConnector Pinout P23 Table 5-25.Front Panel 24-pinConnector PinoutRevision 5-775-78 ReservedRevision < This page intentionally left blank >5-79 Page 6.Power Consumption 6.1Calculated Power Consumption6.2Measured Power Consumption Power ConsumptionSTL2 Server Board TPS DevicesRevision 7.Mechanical Specifications7-83 Mechanical Specifications < This page intentionally left blank >7-84 STL2 Server Board TPS8.Regulatory and Integration Information 8.1Regulatory Compliance8.2Installation Instructions 8.2.1Ensure EMC8.2.3Prevent Power Supply Overload 8.2.4Place Battery Marking on Computer8.2.2.1In Europe 8.2.2.2In the United States8.2.6Installation Precautions 8.3Environmental Limits8.2.5Use Only for Intended Applications 8.3.1System Office Environment8.3.2System Environmental Testing ∙Temperature Operating and Non-Operating∙Humidity Non-Operating ∙Shock Packaged and Unpackaged< This page intentionally left blank > 8-90Regulatory and Integration Information STL2 Server Board TPSGlossary RevisionReference Documents Index RevisionSee POST, 3-22, 3-24, 3-25, 4-29,4- 30, 4-33, Revision