Basic Input Output System (BIOS)

STL2 Server Board TPS

The following code fragment shows the header and format for a user binary:

 

db

55h, 0AAh, 20h

; 16KB USER Area

MyCode

PROC

FAR

; MUST be a FAR procedure

 

db

CBh

; Far return instruction

 

db

04h

; Bit map to define call points, a 1

 

 

 

; in any bit specifies

 

 

 

; that the BIOS is called at that

 

 

 

; scan point in POST

 

db

CBh

; First transfer address used to

 

 

 

; point to user binary extension

 

 

 

; structure

 

dw

?

; Word Pointer to extension

 

 

 

; structure

 

dw

0

; Reserved

 

JMP

ErrRet

; This is a list of 7 transfer

 

 

 

; addresses, one for each

 

JMP

ErrRet

; bit in the bitmap.

 

 

 

; 5 Bytes must be used for each

 

JMP

Start

; JMP to maintain proper offset for

 

 

 

; each entry. Unused entry JMP’s

 

 

 

; should be filled with 5 byte

 

 

 

; filler or JMP to a RETF

 

JMP

ErrRet

;

 

JMP

ErrRet

 

 

JMP

ErrRet

 

 

JMP

ErrRet

 

4.5.2.2Scan Point Definitions

The table below defines the bitmap for each scan point, indicating when the scan point occurs and which resources are available (RAM, stack, binary data area, video, and keyboard).

Table 4-21. User Binary Area Scan Point Definitions

Scan Point

Mask

RAM/Stack/BDA

Video/Keyboard

 

 

 

 

Near pointer to the user binary extension structure, mask bit is 0 if

01h

Not applicable

Not applicable

this structure is not present. Instead of a jump instruction the scan

 

 

 

address (offset 5) contains an 0CB followed by a near pointer.

 

 

 

Obsolete. No action taken.

02h

NA

NA

 

 

 

 

This scan occurs immediately after video initialization.

04h

Yes

Yes

 

 

 

 

This scan occurs immediately before video initialization.

08h

Yes

No

 

 

 

 

This scan occurs on POST error. On entry, BX contains the

10h

Yes

Yes

number of the POST error.

 

 

 

 

 

 

 

This final scan occurs immediately prior to the INT 19 for normal

20h

Yes

Yes

boot and allows one to completely circumvent the normal INT 19

 

 

 

boot if desired.

 

 

 

 

 

 

 

This scan occurs immediately before the normal option ROM

40h

Yes

Yes

scan.

 

 

 

 

 

 

 

This scan occurs immediately following the option ROM area

80h

Yes

Yes

 

 

 

 

4-46

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Image 54
Intel STL2 manual User Binary Area Scan Point Definitions, Scan Point Mask RAM/Stack/BDA Video/Keyboard

STL2 specifications

The Intel STL2, known as the Intel Storage Technology Level 2, is a robust solution designed to elevate storage management and performance for enterprise-level applications. This next-generation system is specifically tailored for organizations that demand high reliability, scalability, and efficiency in their storage solutions.

One of the primary features of the Intel STL2 is its advanced data protection mechanisms. With integrated RAID (Redundant Array of Independent Disks) support, it ensures that data remains safe, even in the event of hardware failure. RAID configurations can be easily set up and managed, allowing businesses to choose the right balance between performance and redundancy based on their unique requirements.

In terms of performance, the STL2 leverages cutting-edge SSD (Solid State Drive) integration to provide high-speed data access and reduced latency. This capability is essential for modern applications that require quick retrieval of large volumes of data, making it suitable for environments like data analytics, AI, and cloud computing.

Scalability is another significant characteristic of the Intel STL2. It is designed to grow alongside an organization’s needs, supporting a diverse range of storage architectures. Whether a company is looking to expand its data center or transition to hybrid cloud solutions, the STL2 can accommodate additional storage resources effortlessly, ensuring that performance does not degrade as storage demands increase.

Moreover, the STL2 features advanced automation and management tools that simplify storage operations. The system allows for real-time monitoring and analytics, providing insights into storage health, performance metrics, and capacity forecasts. This level of visibility enables IT teams to optimize resource utilization and proactively address potential issues before they become critical.

Another notable technology integrated into the STL2 is Intel’s Open Storage Architecture, which promotes interoperability with various software and hardware platforms. This open approach facilitates seamless integrations with existing systems and enhances flexibility within dynamic IT environments.

Lastly, Intel STL2 prioritizes energy efficiency. Its design minimizes power consumption without sacrificing performance, helping organizations reduce their operational costs and carbon footprint.

In summary, the Intel STL2 stands out in the competitive landscape of storage solutions with its focus on data protection, high performance, scalability, advanced management features, open architecture compatibility, and energy efficiency. These characteristics make it an ideal choice for businesses looking to enhance their data storage capabilities in a rapidly evolving digital landscape.