Memory
The four DIMM sockets on board accept 256-, 512-MB or 1-GB DDR (Double Data Rate) SDRAM for a maximum memory capacity of up to 4 GB.
For data integrity, the default setting for the ECC (error correcting code) function of the memory system in BIOS is enabled.
Note: The mainboard supports PC2100/DDR-266 SDRAM DIMMs.
Refer to “Mainboard layout” on page 14 for the location of these DIMM slots on the mainboard.
System chipsets
Server Works chipset
The Server Works GC-SL(Grand Champion – Super Lite) chipset is specifically designed to meet the needs of high performance systems. It consists of the following components:
•CMIC-SL (north bridge) is responsible for communication between the processor, the memory bus, and the IMB (inter-module bus) bus. It runs directly to the processor bus at 133MHz and integrates the functions of main memory controller for DDR. IMB interface unit runs at 400MHz and connects to CIOBX2, and one narrow- version of IMB (Thin-IMB) connects to South Bridge CSB5.
•CIOBX2 (I/O bridge) is a peripheral chip that performs PCI bridging function between the IMB and the 2 PCI-X buses.
•CSB5 (south bridge) integrates the LPC interface that links super I/O functions like keyboard and mouse interface, floppy disk controller, advanced digital data separator, serial port, on-chip 12 mA AT bus drivers, one floppy direct drive support, and IPM (intelligent power management) support.
