Acer Veriton 7600GTR/7600GT/7600V, Veriton 5600GT/5600V manual Advanced Chipset Features, By SPD

Advanced Chipset Features

The following screen shows the Advanced Chipset Features.

The following table describes each Advanced Chipset Features parameter. Settings in boldface are the default and suggested settings.

Parameter	Description	Options
DRAM Timing Selectable	Selects whether DRAM timing is controlled by the	By SPD
	SPD (Serial Presence Detect) EEPROM on the	Manual
	DRAM module. Setting to By SPD enables DRAM
	timings to be determined by BIOS based on the
	configurations on the SPD. Selecting Manual allows
	users to configure the DRAM timings manually.
CAS Latency Time	This controls the timing delay (in clock cycles)	2T, 2.5T, 3T
	before SDRAM starts a read command after
	receiving it. Settings: 2, 2.5, 3 (clocks). 2 (clocks)
	increases the system performance the most while 3
	(clocks) provides the most stable performance.
Active to Precharge Delay	The field specifies the idle cycles before	5T, 6T, 7T, 8T
	precharging an idle bank.
DRAM RAS# to CAS# Delay	This field allows you to set the number of cycles for	2T, 3T, 4T
	a timing delay between the CAS and RAS strobe
	signals, used when DRAM is written to, read from
	or refreshed. Fast speed offers faster performance
	while slow speed offers more stable performance.

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