40 | Configuring the | External DIP Switches |
Note: It is recommended that all unassigned channels be provided an idle termination.
T1 Network
TransmitReceive
FXS 1
FXS 1 Loopback
T24 Network
TransmitReceive
FXS 24
FXS 24 Loopback
The selected DS0 is looped after leaving the framer before reaching the FXS Interface. The CPU is used to control this loopback via the Time Slot Assigner (TSA, a part of the CPU). Subsystems T1 Line Interface Unit, T1 Framer, and CPU are exercised.
Issue 1, September 1998 |
© 1998, ADC Telecommunications, Inc.