Agilent Technologies E8267D PSG, E8257D PSG Data Setup Menu for a Parallel Port Configuration

Peripheral Devices

N5102A Digital Signal Interface Module

Figure 11-1 Data Setup Menu for a Parallel Port Configuration

Least significant bit	Most significant bit	Clock and sample rates
See the PSG User’s Guide for information

The N5102A module clock rate is set using the Clock Rate softkey and has a range of 1 kHz to

400 MHz. The sample rate is automatically calculated and has a range of 1 kHz to 100 MHz. These ranges can be smaller depending on logic type, data parameters, and clock configuration.

Maximum Clock Rates

The N5102A module maximum clock rate depends on the logic and signal type. Table 11- 1 and Table 11- 2 show the warranted rates and the maximum clock rates for the various logic and signal types. Notice that LVDS in the output mode using an IF signal is the only logic type where the warranted and maximum rates are the same.

Table 11-1 Warranted Parallel Output Level Clock Rates and Maximum Clock Rates

Logic Type	Warranted Level Clock Rates				Maximum Clock Rates (typical)
	IQ Signal Type		IF Signal Typea		IQ Signal Type		IF Signal Type
LVTTL and CMOS	100	MHz	100	MHz	150	MHz	150	MHz
LVDS	200	MHz	400	MHz	400	MHz	400	MHz

a.The IF signal type is not available for a serial port configuration.

204 Chapter 11