Agilent Technologies E8257D PSG, E8267D PSG manual Clock Source, Common Frequency Reference

Peripheral Devices

N5102A Digital Signal Interface Module

Clock Source

The clock signal for the N5102A module is provided in one of three ways through the following selections:

•Internal: generated internally in the interface module (requires an external reference)

•External: generated externally through the Ext Clock In connector

•Device: generated externally through the Device Interface connector

The clock source is selected using the N5102A module UI on the signal generator, as shown in Figure 11- 2.

Figure 11-2 Clock Source Selection

External and Device selection: Set to match the clock rate

of the applied clock signal Internal selection: Set the internal clock rate

Internal clock source selection: Set the frequency of the applied reference signal.

When you select a clock source, you must let the N5102A module know the frequency of the clock signal using the Clock Rate softkey. In the internal clock source mode, use this softkey to set the internal clock rate. For device and external clock sources, this softkey must reflect the frequency of the applied clock signal.

When the clock source is Internal, a frequency reference must be applied to the Freq Ref connector. The frequency of this applied signal needs to be specified using the Reference Frequency softkey, unless the current setting matches that of the applied signal.

The selected clock source provides the interface module output clock signal at the Clock Out and the Device Interface connectors.

Common Frequency Reference

The clocking flexibility of the digital signal interface module allows the setting of arbitrary clock rates for the device under test. In general, the clock rate inside the PSG will be different from the interface module clock rate, so the interface module performs a rate conversion. An important aspect of this conversion is to have accurate clock rate information to avoid losing data. The module relies on relative clock accuracy, instead of absolute accuracy, that must be ensured by using a single frequency reference for all clock rates involved in the test setup. This can be implemented in various ways (see the five drawings in Figure 11- 3 on page 209), but whatever way it is implemented, the

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