Procrdy | AMD 10 instruction

AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet

31994A—1 August 2004

Figure 4 shows STPCLK# assertion resulting in the processor in the Stop Grant state and the AMD Athlon system bus disconnected.

STPCLK#

AMD Athlon™

System Bus Stop Grant

CONNECT

PROCRDY

CLKFWDRST

PCI Bus Stop Grant

Figure 4. AMD Athlon™ System Bus Disconnect Sequence in the Stop Grant State

An example of the AMD Athlon system bus disconnect sequence is as follows:

1.The peripheral controller (Southbridge) asserts STPCLK# to place the processor in the Stop Grant state.

2.When the processor recognizes STPCLK# asserted, it enters the Stop Grant state and then issues a Stop Grant special cycle.

3.When the special cycle is received by the Northbridge, it deasserts CONNECT, assuming no probes are pending, initiating a bus disconnect to the processor.

4.The processor responds to the Northbridge by deasserting

PROCRDY.

5.The Northbridge asserts CLKFWDRST to complete the bus disconnect sequence.

6.After the processor is disconnected from the bus, the processor enters a low-power state. The Northbridge passes the Stop Grant special cycle along to the Southbridge.

14

Power Management

Chapter 4

Image 26

AMD 10 manual Procrdy

Contents

Data Sheet Advanced Micro Devices, Inc. All rights reserved Table of Contents Mechanical Data Ordering Information AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Typical AMD Sempron Processor Model 10 System Block Diagram List of Figures Viii List of Tables List of Tables Revision History Date Rev Description Xii Overview Chapter QuantiSpeed Architecture Summary Typical AMD Sempron Processor Model 10 System Block Diagram Overview Interface SignalsSignaling Technology AMD Athlon System Bus Signals Push-Pull PP Drivers Frequency Control Front-Side Bus Autodetect Legacy Logic Symbol DiagramProcessor Model Diode AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Power Management Power Management States Working State Halt State Chapter Power Management Probe State Connect Protocol AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Procrdy Exiting the Stop Grant State and Bus Connect Sequence Diagram Connect State Return internal clocks to full speed and assert Connect Pending Disconnect Disconnect4/CDisconnect request Northbridge Clock Control Cpuid Support AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 256K L2 Cache Specifications Duty Cycle Parameter Description Minimum MaximumClock Frequency 333 FSB AMD Athlon System Bus AC Characteristics 333 FSB AMD Athlon System Bus DC Characteristics FSB AMD Athlon System Bus DC Characteristics Electrical Data Interface Signal GroupingsInterface Signal Groupings Conventions VID40 DC Characteristics Voltage Identification VID40 Frequency Identification FID30 Vcca AC and DC CharacteristicsFID30 DC Characteristics Decoupling Vcccore Characteristics Vcccore AC and DC Characteristics Vcccore Voltage Waveform Absolute Ratings Absolute Ratings Sysclk and SYSCLK# DC Characteristics Sysclk and SYSCLK# DC Characteristics General AC and DC Characteristics General AC and DC Characteristics Signal Fall Time Sync Input Setup TimeSignal Rise Time Sync Input Hold Time Open Drain Test Circuit 50 Ω ±3% Open-Drain Pin IOL = Output Current2 Thermal Diode Electrical Characteristics Thermal Diode CharacteristicsCharacteristics Thermal Diode AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Guidelines for Platform Thermal Protection of the Processor Apic Pins AC and DC CharacteristicsApic Pin AC and DC Characteristics Setup Time Hold Time Signal and Power-Up Requirements Power-Up Requirements Pwrok AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Selection FID30 Processor Warm Reset RequirementsClock Multiplier Mechanical Loading Mechanical DataDie Loading Location Dynamic MAX Static MAX Units Die Surface 100 Letter or Minimum Maximum 453 Chapter Mechanical Data Dimension 49.27 49.78 D1/E1 45.72 BSC 917 REF 42 REF 977 Chapter Mechanical Data AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Pin Diagram and Pin Name Abbreviations Pin Descriptions Model AMD Sempron Processor Model 10 Pin Diagram-Bottomside View AMD Sempron Processor Pin Name Abbreviations AC31 Abbreviation Full Name Pin Q31 S31 U31 U37 W31 Y31 Y33AA31 AD30 AG37 AE33AJ35 AL33 E27 W33J35 E15 F32 F24F28 F34 AM10 AK34AK36 AM14 V34 V30V32 V36 Pin List No Pin Cross-Reference by Pin LocationPin Name A35 SDATA40# A37 SDATA30# E33 NC Pin E35 SDATA31# E37 SDATA22# SDATA52# E11 SDATA50# E13 SDATA49# E15E29 SDATA33# E31 SDATA32# Pin Name NC Pin F10 NC Pin VID4 J31 J33 SDATA19# J35 NC Pin H10 H12H28 NC Pin H30 H32 H34 J37 SDATA29# S35 SDATA15# S37 Key Pin Q31 NC Pin Q33 SDATA24# Q35 SDATA17# Q37 SDATA16#S31 NC Pin S33 U31 NC Pin U33 FID2 FID3 NC Pin Key Pin Y31 Y33 Y35 FID0 FID1NC Pin W31 W33 Y37 SDATA12# NC Pin AF10 AF12 NC Pin AD30 AD32AE31 NC Pin AE33 AF20 AJ27 NC Pin AJ29 AH30 FSBSense1 AH32NC Pin AJ11 AJ13 Analog AJ15 AJ17 AJ19 AJ21 NC Pin AK10 NC Pin AN11 AN13 AL25 NC Pin AL27 AL29NC Pin AM10 AN25 NC Pin AN27 AN29 Detailed Pin Descriptions Pins Sysclk PinsCOREFB# Pins Connect Pin FID30 Pins FID30 Clock Multiplier Encodings IGNNE# Pin Front-Side Bus Sense Truth TableFLUSH# Pin INIT# Pin Key Pins Jtag PinsK7CLKOUT# Pins NC Pins Thermdc Pins SADDOUT10# PinsScan Pins Pwrok Pin VID40 Code to Voltage Definition VID40 PinsVrefsys Pin ZN and ZP Pins AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Ordering Information Standard AMD Sempron Processor Model 10 Products AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Ideal Diode Equation Constants and Variables for the Ideal Diode Equation Temperature Offset Correction ⎛--- I-- high------ ⎞ AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Signals and Bits Appendix B Data Terminology Abbreviation Meaning Abbreviations and AcronymsAbbreviations Acronyms API NMI VGA Related Publications AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet