Intr Pin, Jtag Pins, K7CLKOUT# Pins, Key Pins, NC Pins | AMD 10

AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet

31994A—1 August 2004

INTR Pin	INTR is an input from the system that causes the processor to
	start an interrupt acknowledge transaction that fetches the
	8-bit interrupt vector and starts execution at that location.
JTAG Pins	TCK, TMS, TDI, TRST#, and TDO are the JTAG interface.
	Connect these pins directly to the motherboard debug
	connector. Pull TDI, TCK, TMS, and TRST# up to VCC_CORE with
	pullup resistors.
K7CLKOUT and	K7CLKOUT and K7CLKOUT# are each run for two to three
K7CLKOUT# Pins	inches and then terminated with a resistor pair: 100 ohms to
	VCC_CORE and 100 ohms to VSS. The effective termination
	resistance and voltage are 50 ohms and VCC_CORE /2.
Key Pins	These 16 locations are for processor type keying for forwards
	and backwards compatibility (G7, G9, G15, G17, G23, G25, N7,
	Q7, Y7, AA7, AG7, AG9, AG15, AG17, AG27, and AG29).
	Motherboard designers should treat key pins like NC (No
	Connect) pins. A socket designer has the option of creating a
	top mold piece that allows PGA key pins only where designated.
	However, sockets that populate all 16 key pins must be allowed,
	so the motherboard must always provide for pins at all key pin
	locations.
	See “NC Pins“ for more information.
NC Pins	The motherboard should provide a plated hole for an NC pin.
	The pin hole should not be electrically connected to anything.
NMI Pin	NMI is an input from the system that causes a non-maskable
	interrupt.
PGA Orientation Pins	No pin is present at pin locations A1 and AN1. Motherboard
	designers should not allow for a PGA socket pin at these
	locations.
	For more information, see the AMD Athlon™ Processor-Based
	Motherboard Design Guide, order# 24363.
PLL Bypass and Test	PLLTEST#, PLLBYPASS#, PLLMON1, PLLMON2,
Pins	PLLBYPASSCLK, and PLLBYPASSCLK# are the PLL bypass
	and test interface. This interface is tied disabled on the
	motherboard. All six pin signals are routed to the debug
	connector. All four processor inputs (PLLTEST#, PLLBYPASS#,
	PLLMON1, and PLLMON2) are tied to VCC_CORE with pullup
	resistors.

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Pin Descriptions

Chapter 10

Image 84

AMD 10 Intr Pin, Jtag Pins, K7CLKOUT# Pins, Key Pins, NC Pins, NMI Pin, PGA Orientation Pins, PLL Bypass and Test

Contents

Data Sheet Advanced Micro Devices, Inc. All rights reserved Table of Contents Mechanical Data Ordering Information AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Typical AMD Sempron Processor Model 10 System Block Diagram List of Figures Viii List of Tables List of Tables Revision History Date Rev Description Xii Overview Chapter QuantiSpeed Architecture Summary Typical AMD Sempron Processor Model 10 System Block Diagram Interface Signals Signaling TechnologyOverview AMD Athlon System Bus Signals Push-Pull PP Drivers Logic Symbol Diagram Processor ModelFrequency Control Front-Side Bus Autodetect Legacy Diode AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Power Management Power Management States Working State Halt State Chapter Power Management Probe State Connect Protocol AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Procrdy Exiting the Stop Grant State and Bus Connect Sequence Diagram Connect State Connect Pending Disconnect Disconnect4/C Disconnect requestReturn internal clocks to full speed and assert Northbridge Clock Control Cpuid Support AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 256K L2 Cache Specifications Parameter Description Minimum Maximum Clock FrequencyDuty Cycle 333 FSB AMD Athlon System Bus AC Characteristics 333 FSB AMD Athlon System Bus DC Characteristics FSB AMD Athlon System Bus DC Characteristics Interface Signal Groupings Interface Signal GroupingsElectrical Data Conventions VID40 DC Characteristics Voltage Identification VID40 Vcca AC and DC Characteristics FID30 DC CharacteristicsFrequency Identification FID30 Decoupling Vcccore Characteristics Vcccore AC and DC Characteristics Vcccore Voltage Waveform Absolute Ratings Absolute Ratings Sysclk and SYSCLK# DC Characteristics Sysclk and SYSCLK# DC Characteristics General AC and DC Characteristics General AC and DC Characteristics Sync Input Setup Time Signal Rise TimeSignal Fall Time Sync Input Hold Time Open Drain Test Circuit 50 Ω ±3% Open-Drain Pin IOL = Output Current2 Thermal Diode Characteristics CharacteristicsThermal Diode Electrical Characteristics Thermal Diode AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Apic Pins AC and DC Characteristics Apic Pin AC and DC CharacteristicsGuidelines for Platform Thermal Protection of the Processor Setup Time Hold Time Signal and Power-Up Requirements Power-Up Requirements Pwrok AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Processor Warm Reset Requirements Clock MultiplierSelection FID30 Mechanical Data Die LoadingMechanical Loading Location Dynamic MAX Static MAX Units Die Surface 100 Letter or Minimum Maximum 453 Chapter Mechanical Data Dimension 49.27 49.78 D1/E1 45.72 BSC 917 REF 42 REF 977 Chapter Mechanical Data AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Pin Diagram and Pin Name Abbreviations Pin Descriptions Model AMD Sempron Processor Model 10 Pin Diagram-Bottomside View AMD Sempron Processor Pin Name Abbreviations Abbreviation Full Name Pin Q31 S31 U31 U37 W31 Y31 Y33 AA31AC31 AD30 AE33 AJ35AG37 AL33 W33 J35E27 E15 F24 F28F32 F34 AK34 AK36AM10 AM14 V30 V32V34 V36 Pin List Cross-Reference by Pin Location Pin NameNo Pin A35 SDATA40# A37 SDATA30# SDATA52# E11 SDATA50# E13 SDATA49# E15 E29 SDATA33# E31 SDATA32# Pin NameE33 NC Pin E35 SDATA31# E37 SDATA22# NC Pin F10 NC Pin H10 H12 H28 NC Pin H30 H32 H34NC Pin VID4 J31 J33 SDATA19# J35 J37 SDATA29# Key Pin Q31 NC Pin Q33 SDATA24# Q35 SDATA17# Q37 SDATA16# S31 NC Pin S33S35 SDATA15# S37 U31 NC Pin U33 FID0 FID1 NC Pin W31 W33FID2 FID3 NC Pin Key Pin Y31 Y33 Y35 Y37 SDATA12# NC Pin AD30 AD32 AE31 NC Pin AE33NC Pin AF10 AF12 AF20 AH30 FSBSense1 AH32 NC Pin AJ11 AJ13 Analog AJ15 AJ17 AJ19 AJ21AJ27 NC Pin AJ29 NC Pin AK10 AL25 NC Pin AL27 AL29 NC Pin AM10NC Pin AN11 AN13 AN25 NC Pin AN27 AN29 Detailed Pin Descriptions Sysclk Pins COREFB# PinsPins Connect Pin FID30 Pins FID30 Clock Multiplier Encodings Front-Side Bus Sense Truth Table FLUSH# PinIGNNE# Pin INIT# Pin Jtag Pins K7CLKOUT# PinsKey Pins NC Pins SADDOUT10# Pins Scan PinsThermdc Pins Pwrok Pin VID40 Pins Vrefsys PinVID40 Code to Voltage Definition ZN and ZP Pins AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Ordering Information Standard AMD Sempron Processor Model 10 Products AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Ideal Diode Equation Constants and Variables for the Ideal Diode Equation Temperature Offset Correction ⎛--- I-- high------ ⎞ AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Signals and Bits Appendix B Data Terminology Abbreviations and Acronyms AbbreviationsAbbreviation Meaning Acronyms API NMI VGA Related Publications AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet