AMD 10 manual Signal and Power-Up Requirements

31994A —1August 2004 AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet

8 Signal and Power-Up Requirements

The AMD Sempron™ processor model 10 is designed to provide functional operation if the voltage and temperature parameters are within the limits of normal operating ranges.

8.1Power-Up Requirements

Signal Sequence and Figure 12 shows the relationship between key signals in the

Timing Description system during a power-up sequence. This figure details the requirements of the processor.

3.3 V Supply
VCCA (2.5 V)
(for PLL)
VCC_CORE
			2
(Processor Core)		1				Warm reset
RESET#				6
						condition
NB_RESET#				4
PWROK	5
					8
	7

FID[3:0]

3

System Clock

Figure 12. Signal Relationship Requirements During Power-Up Sequence

Notes: 1. Figure 12 represents several signals generically by using names not necessarily consistent with any pin lists or schematics.

2.Requirements 1–8 in Figure 12 are described in “Power-Up Timing Requirements” on page 40.

Chapter 8 Signal and Power-Up Requirements 39