Probe State, Connect Protocol | AMD 10 guide

AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet

31994A—1 August 2004

In C2, probes are allowed, as shown in Figure 3 on page 9

	The Stop Grant state is also entered for the S1, Powered On
	Suspend, system sleep state based on a write to the SLP_TYP
	and SLP_EN fields in the ACPI-defined Power Management 1
	control register in the Southbridge. During the S1 Sleep state,
	system software ensures no bus master or probe activity occurs.
	The Southbridge deasserts STPCLK# and brings the processor
	out of the S1 Stop Grant state when any enabled resume event
	occurs.
Probe State	The Probe state is entered when the Northbridge connects the
	AMD Athlon system bus to probe the processor (for example, to
	snoop the processor caches) when the processor is in the Halt or
	Stop Grant state. When in the Probe state, the processor
	responds to a probe cycle in the same manner as when it is in
	the Working state. When the probe has been serviced, the
	processor returns to the same state as when it entered the
	Probe state (Halt or Stop Grant state). When probe activity is
	completed the processor only returns to a low-power state after
	the Northbridge disconnects the AMD Athlon system bus again.

4.2	Connect and Disconnect Protocol
		Significant power savings of the processor only occur if the
		processor is disconnected from the system bus by the
		Northbridge while in the Halt or Stop Grant state. The
		Northbridge can optionally initiate a bus disconnect upon the
		receipt of a Halt or Stop Grant special cycle. The option of
		disconnecting is controlled by an enable bit in the Northbridge.
		If the Northbridge requires the processor to service a probe
		after the system bus has been disconnected, it must first
		initiate a system bus connect.
Connect Protocol		In addition to the legacy STPCLK# signal and the Halt and Stop
		Grant special cycles, the AMD Athlon system bus connect
		protocol includes the CONNECT, PROCRDY, and CLKFWDRST
		signals and a Connect special cycle.
		AMD Athlon system bus disconnects are initiated by the
		Northbridge in response to the receipt of a Halt or Stop Grant.
		Reconnect is initiated by the processor in response to an

12		Power Management	Chapter 4

Image 24

AMD 10 manual Probe State, Connect Protocol

Contents

Data Sheet Advanced Micro Devices, Inc. All rights reserved Table of Contents Mechanical Data Ordering Information AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Typical AMD Sempron Processor Model 10 System Block Diagram List of Figures Viii List of Tables List of Tables Revision History Date Rev Description Xii Overview Chapter QuantiSpeed Architecture Summary Typical AMD Sempron Processor Model 10 System Block Diagram Interface Signals Signaling TechnologyOverview AMD Athlon System Bus Signals Push-Pull PP Drivers Logic Symbol Diagram Processor ModelFrequency Control Front-Side Bus Autodetect Legacy Diode AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Power Management Power Management States Working State Halt State Chapter Power Management Probe State Connect Protocol AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Procrdy Exiting the Stop Grant State and Bus Connect Sequence Diagram Connect State Connect Pending Disconnect Disconnect4/C Disconnect requestReturn internal clocks to full speed and assert Northbridge Clock Control Cpuid Support AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 256K L2 Cache Specifications Parameter Description Minimum Maximum Clock FrequencyDuty Cycle 333 FSB AMD Athlon System Bus AC Characteristics 333 FSB AMD Athlon System Bus DC Characteristics FSB AMD Athlon System Bus DC Characteristics Interface Signal Groupings Interface Signal GroupingsElectrical Data Conventions VID40 DC Characteristics Voltage Identification VID40 Vcca AC and DC Characteristics FID30 DC CharacteristicsFrequency Identification FID30 Decoupling Vcccore Characteristics Vcccore AC and DC Characteristics Vcccore Voltage Waveform Absolute Ratings Absolute Ratings Sysclk and SYSCLK# DC Characteristics Sysclk and SYSCLK# DC Characteristics General AC and DC Characteristics General AC and DC Characteristics Sync Input Setup Time Signal Rise TimeSignal Fall Time Sync Input Hold Time Open Drain Test Circuit 50 Ω ±3% Open-Drain Pin IOL = Output Current2 Thermal Diode Characteristics CharacteristicsThermal Diode Electrical Characteristics Thermal Diode AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Apic Pins AC and DC Characteristics Apic Pin AC and DC CharacteristicsGuidelines for Platform Thermal Protection of the Processor Setup Time Hold Time Signal and Power-Up Requirements Power-Up Requirements Pwrok AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Processor Warm Reset Requirements Clock MultiplierSelection FID30 Mechanical Data Die LoadingMechanical Loading Location Dynamic MAX Static MAX Units Die Surface 100 Letter or Minimum Maximum 453 Chapter Mechanical Data Dimension 49.27 49.78 D1/E1 45.72 BSC 917 REF 42 REF 977 Chapter Mechanical Data AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Pin Diagram and Pin Name Abbreviations Pin Descriptions Model AMD Sempron Processor Model 10 Pin Diagram-Bottomside View AMD Sempron Processor Pin Name Abbreviations Abbreviation Full Name Pin Q31 S31 U31 U37 W31 Y31 Y33 AA31AC31 AD30 AE33 AJ35AG37 AL33 W33 J35E27 E15 F24 F28F32 F34 AK34 AK36AM10 AM14 V30 V32V34 V36 Pin List Cross-Reference by Pin Location Pin NameNo Pin A35 SDATA40# A37 SDATA30# SDATA52# E11 SDATA50# E13 SDATA49# E15 E29 SDATA33# E31 SDATA32# Pin NameE33 NC Pin E35 SDATA31# E37 SDATA22# NC Pin F10 NC Pin H10 H12 H28 NC Pin H30 H32 H34NC Pin VID4 J31 J33 SDATA19# J35 J37 SDATA29# Key Pin Q31 NC Pin Q33 SDATA24# Q35 SDATA17# Q37 SDATA16# S31 NC Pin S33S35 SDATA15# S37 U31 NC Pin U33 FID0 FID1 NC Pin W31 W33FID2 FID3 NC Pin Key Pin Y31 Y33 Y35 Y37 SDATA12# NC Pin AD30 AD32 AE31 NC Pin AE33NC Pin AF10 AF12 AF20 AH30 FSBSense1 AH32 NC Pin AJ11 AJ13 Analog AJ15 AJ17 AJ19 AJ21AJ27 NC Pin AJ29 NC Pin AK10 AL25 NC Pin AL27 AL29 NC Pin AM10NC Pin AN11 AN13 AN25 NC Pin AN27 AN29 Detailed Pin Descriptions Sysclk Pins COREFB# PinsPins Connect Pin FID30 Pins FID30 Clock Multiplier Encodings Front-Side Bus Sense Truth Table FLUSH# PinIGNNE# Pin INIT# Pin Jtag Pins K7CLKOUT# PinsKey Pins NC Pins SADDOUT10# Pins Scan PinsThermdc Pins Pwrok Pin VID40 Pins Vrefsys PinVID40 Code to Voltage Definition ZN and ZP Pins AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Ordering Information Standard AMD Sempron Processor Model 10 Products AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Ideal Diode Equation Constants and Variables for the Ideal Diode Equation Temperature Offset Correction ⎛--- I-- high------ ⎞ AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Signals and Bits Appendix B Data Terminology Abbreviations and Acronyms AbbreviationsAbbreviation Meaning Acronyms API NMI VGA Related Publications AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet