Sync Input Setup Time, Sync Input Hold Time | AMD 10 manual

31994A —1August 2004

AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet

Table 12. General AC and DC Characteristics (continued)

Symbol		Parameter Description	Condition		Min		Max	Units		Notes

TSU		Sync Input Setup Time			2.0			ns		4, 5
THD		Sync Input Hold Time			0.0			ps		4, 5
TDELAY		Output Delay with respect to RSTCLK			0.0		6.1	ns		5
TBIT		Input Time to Acquire			20.0			ns		7, 8
TRPT		Input Time to Reacquire			40.0			ns		9–13
TRISE		Signal Rise Time			1.0		3.0	V/ns		6
TFALL		Signal Fall Time			1.0		3.0	V/ns		6
CPIN		Pin Capacitance			4		12	pF
TVALID		Time to data valid					100	ns		14
Notes:
1.	Characterized across DC supply voltage range.
2.	Values specified at nominal VCC_CORE . Scale parameters between VCC_CORE. minimum and VCC_CORE. maximum.
3.	IOL and IOH are measured at VOL maximum and VOH minimum, respectively.
4.	Synchronous inputs/outputs are specified with respect to RSTCLK and RSTCK# at the pins.
5.	These are aggregate numbers.
6.	Edge rates indicate the range over which inputs were characterized.
7.	In asynchronous operation, the signal must persist for this time to enable capture.
8.	This value assumes RSTCLK period is 10 ns ==> TBIT = 2*fRST.
9.	The approximate value for standard case in normal mode operation.
10.	This value is dependent on RSTCLK frequency, divisors, Low Power mode, and core frequency.
11.	Reassertions of the signal within this time are not guaranteed to be seen by the core.
12.	This value assumes that the skew between RSTCLK and K7CLKOUT is much less than one phase.
13.	This value assumes RSTCLK and K7CLKOUT are running at the same frequency, though the processor is capable of other
	configurations.
14.	Time to valid is for any open-drain pins. See requirements 7 and 8			in the “Power-Up Timing Requirements“ chapter for more
	information.

Chapter 7

Electrical Data

33

Image 45

AMD 10 manual Sync Input Setup Time, Sync Input Hold Time, Input Time to Acquire, Input Time to Reacquire, Signal Rise Time

Contents

Data Sheet Advanced Micro Devices, Inc. All rights reserved Table of Contents Mechanical Data Ordering Information AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet List of Figures Typical AMD Sempron Processor Model 10 System Block Diagram Viii List of Tables List of Tables Date Rev Description Revision History Xii Overview Chapter QuantiSpeed Architecture Summary Typical AMD Sempron Processor Model 10 System Block Diagram Interface Signals Signaling TechnologyOverview Push-Pull PP Drivers AMD Athlon System Bus Signals Processor Model Logic Symbol DiagramFrequency Control Front-Side Bus Autodetect Legacy Diode AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Power Management States Power Management Halt State Working State Chapter Power Management Connect Protocol Probe State AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Procrdy Exiting the Stop Grant State and Bus Connect Sequence Connect State Diagram Disconnect request Connect Pending Disconnect Disconnect4/CReturn internal clocks to full speed and assert Northbridge Clock Control Cpuid Support AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 256K L2 Cache Specifications Parameter Description Minimum Maximum Clock FrequencyDuty Cycle 333 FSB AMD Athlon System Bus AC Characteristics FSB AMD Athlon System Bus DC Characteristics 333 FSB AMD Athlon System Bus DC Characteristics Interface Signal Groupings Interface Signal GroupingsElectrical Data Conventions Voltage Identification VID40 VID40 DC Characteristics FID30 DC Characteristics Vcca AC and DC CharacteristicsFrequency Identification FID30 Decoupling Vcccore AC and DC Characteristics Vcccore Characteristics Vcccore Voltage Waveform Absolute Ratings Absolute Ratings Sysclk and SYSCLK# DC Characteristics Sysclk and SYSCLK# DC Characteristics General AC and DC Characteristics General AC and DC Characteristics Signal Rise Time Sync Input Setup TimeSignal Fall Time Sync Input Hold Time 50 Ω ±3% Open-Drain Pin IOL = Output Current2 Open Drain Test Circuit Characteristics Thermal Diode CharacteristicsThermal Diode Electrical Characteristics Thermal Diode AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Apic Pins AC and DC Characteristics Apic Pin AC and DC CharacteristicsGuidelines for Platform Thermal Protection of the Processor Hold Time Setup Time Power-Up Requirements Signal and Power-Up Requirements Pwrok AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Processor Warm Reset Requirements Clock MultiplierSelection FID30 Die Loading Mechanical DataMechanical Loading Location Dynamic MAX Static MAX Units Die Surface 100 453 Letter or Minimum Maximum Chapter Mechanical Data Dimension 49.27 49.78 D1/E1 45.72 BSC 917 REF 42 REF 977 Chapter Mechanical Data AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Pin Descriptions Pin Diagram and Pin Name Abbreviations Model AMD Sempron Processor AMD Sempron Processor Model 10 Pin Diagram-Bottomside View Pin Name Abbreviations AA31 Abbreviation Full Name Pin Q31 S31 U31 U37 W31 Y31 Y33AC31 AD30 AJ35 AE33AG37 AL33 J35 W33E27 E15 F28 F24F32 F34 AK36 AK34AM10 AM14 V32 V30V34 V36 Pin List Pin Name Cross-Reference by Pin LocationNo Pin A35 SDATA40# A37 SDATA30# E29 SDATA33# E31 SDATA32# Pin Name SDATA52# E11 SDATA50# E13 SDATA49# E15E33 NC Pin E35 SDATA31# E37 SDATA22# NC Pin F10 H28 NC Pin H30 H32 H34 NC Pin H10 H12NC Pin VID4 J31 J33 SDATA19# J35 J37 SDATA29# S31 NC Pin S33 Key Pin Q31 NC Pin Q33 SDATA24# Q35 SDATA17# Q37 SDATA16#S35 SDATA15# S37 U31 NC Pin U33 NC Pin W31 W33 FID0 FID1FID2 FID3 NC Pin Key Pin Y31 Y33 Y35 Y37 SDATA12# AE31 NC Pin AE33 NC Pin AD30 AD32NC Pin AF10 AF12 AF20 NC Pin AJ11 AJ13 Analog AJ15 AJ17 AJ19 AJ21 AH30 FSBSense1 AH32AJ27 NC Pin AJ29 NC Pin AK10 NC Pin AM10 AL25 NC Pin AL27 AL29NC Pin AN11 AN13 AN25 NC Pin AN27 AN29 Detailed Pin Descriptions COREFB# Pins Sysclk PinsPins Connect Pin FID30 Clock Multiplier Encodings FID30 Pins FLUSH# Pin Front-Side Bus Sense Truth TableIGNNE# Pin INIT# Pin K7CLKOUT# Pins Jtag PinsKey Pins NC Pins Scan Pins SADDOUT10# PinsThermdc Pins Pwrok Pin VID40 Pins Vrefsys PinVID40 Code to Voltage Definition ZN and ZP Pins AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Standard AMD Sempron Processor Model 10 Products Ordering Information AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Constants and Variables for the Ideal Diode Equation Ideal Diode Equation Temperature Offset Correction ⎛--- I-- high------ ⎞ AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Appendix B Signals and Bits Data Terminology Abbreviations and Acronyms AbbreviationsAbbreviation Meaning API Acronyms NMI VGA Related Publications AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet