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AMD 10 manual Exiting the Stop Grant State and Bus Connect Sequence

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31994A —1August 2004

AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet

Figure 5 shows the signal sequence of events that takes the processor out of the Stop Grant state, connects the processor to the AMD Athlon system bus, and puts the processor into the Working state.

Figure 5. Exiting the Stop Grant State and Bus Connect Sequence

The following sequence of events removes the processor from the Stop Grant state and connects it to the system bus:

1.The Southbridge deasserts STPCLK#, informing the processor of a wake event.

2.When the processor recognizes STPCLK# deassertion, it exits the low-power state and asserts PROCRDY, notifying the Northbridge to connect to the bus.

3.The Northbridge asserts CONNECT.

4.The Northbridge deasserts CLKFWDRST, synchronizing the forwarded clocks between the processor and the Northbridge.

5.The processor issues a Connect special cycle on the system bus and resumes operating system and application code execution.

Chapter 4

Power Management

15

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AMD 10 manual Exiting the Stop Grant State and Bus Connect Sequence

Contents

Data Sheet Advanced Micro Devices, Inc. All rights reserved Table of Contents Mechanical Data Ordering Information AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet List of Figures Typical AMD Sempron Processor Model 10 System Block DiagramViii List of Tables List of Tables Date Rev Description Revision HistoryXii Overview Chapter QuantiSpeed Architecture Summary Typical AMD Sempron Processor Model 10 System Block Diagram Interface Signals Signaling TechnologyOverview Push-Pull PP Drivers AMD Athlon System Bus SignalsDiode Logic Symbol DiagramProcessor Model Frequency Control Front-Side Bus Autodetect LegacyAMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Power Management States Power ManagementHalt State Working StateChapter Power Management Connect Protocol Probe StateAMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Procrdy Exiting the Stop Grant State and Bus Connect Sequence Connect State DiagramNorthbridge Connect Pending Disconnect Disconnect4/CDisconnect request Return internal clocks to full speed and assertClock Control Cpuid Support AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 256K L2 Cache Specifications Parameter Description Minimum Maximum Clock FrequencyDuty Cycle 333 FSB AMD Athlon System Bus AC Characteristics FSB AMD Athlon System Bus DC Characteristics 333 FSB AMD Athlon System Bus DC CharacteristicsConventions Interface Signal GroupingsInterface Signal Groupings Electrical DataVoltage Identification VID40 VID40 DC CharacteristicsDecoupling Vcca AC and DC CharacteristicsFID30 DC Characteristics Frequency Identification FID30Vcccore AC and DC Characteristics Vcccore CharacteristicsVcccore Voltage Waveform Absolute Ratings Absolute RatingsSysclk and SYSCLK# DC Characteristics Sysclk and SYSCLK# DC CharacteristicsGeneral AC and DC Characteristics General AC and DC CharacteristicsSync Input Hold Time Sync Input Setup TimeSignal Rise Time Signal Fall Time50 Ω ±3% Open-Drain Pin IOL = Output Current2 Open Drain Test CircuitThermal Diode Thermal Diode CharacteristicsCharacteristics Thermal Diode Electrical CharacteristicsAMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Apic Pins AC and DC Characteristics Apic Pin AC and DC CharacteristicsGuidelines for Platform Thermal Protection of the Processor Hold Time Setup TimePower-Up Requirements Signal and Power-Up RequirementsPwrok AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Processor Warm Reset Requirements Clock MultiplierSelection FID30 Location Dynamic MAX Static MAX Units Die Surface 100 Mechanical DataDie Loading Mechanical Loading453 Letter or Minimum MaximumChapter Mechanical Data Dimension 49.27 49.78 D1/E1 45.72 BSC 917 REF 42 REF 977 Chapter Mechanical Data AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Pin Descriptions Pin Diagram and Pin Name AbbreviationsModel AMD Sempron Processor AMD Sempron Processor Model 10 Pin Diagram-Bottomside ViewPin Name Abbreviations AD30 Abbreviation Full Name Pin Q31 S31 U31 U37 W31 Y31 Y33AA31 AC31AL33 AE33AJ35 AG37E15 W33J35 E27F34 F24F28 F32AM14 AK34AK36 AM10V36 V30V32 V34Pin List A35 SDATA40# A37 SDATA30# Cross-Reference by Pin LocationPin Name No PinNC Pin F10 SDATA52# E11 SDATA50# E13 SDATA49# E15E29 SDATA33# E31 SDATA32# Pin Name E33 NC Pin E35 SDATA31# E37 SDATA22#J37 SDATA29# NC Pin H10 H12H28 NC Pin H30 H32 H34 NC Pin VID4 J31 J33 SDATA19# J35U31 NC Pin U33 Key Pin Q31 NC Pin Q33 SDATA24# Q35 SDATA17# Q37 SDATA16#S31 NC Pin S33 S35 SDATA15# S37Y37 SDATA12# FID0 FID1NC Pin W31 W33 FID2 FID3 NC Pin Key Pin Y31 Y33 Y35AF20 NC Pin AD30 AD32AE31 NC Pin AE33 NC Pin AF10 AF12NC Pin AK10 AH30 FSBSense1 AH32NC Pin AJ11 AJ13 Analog AJ15 AJ17 AJ19 AJ21 AJ27 NC Pin AJ29AN25 NC Pin AN27 AN29 AL25 NC Pin AL27 AL29NC Pin AM10 NC Pin AN11 AN13Detailed Pin Descriptions Connect Pin Sysclk PinsCOREFB# Pins PinsFID30 Clock Multiplier Encodings FID30 PinsINIT# Pin Front-Side Bus Sense Truth TableFLUSH# Pin IGNNE# PinNC Pins Jtag PinsK7CLKOUT# Pins Key PinsPwrok Pin SADDOUT10# PinsScan Pins Thermdc PinsVID40 Pins Vrefsys PinVID40 Code to Voltage Definition ZN and ZP Pins AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Standard AMD Sempron Processor Model 10 Products Ordering InformationAMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Constants and Variables for the Ideal Diode Equation Ideal Diode EquationTemperature Offset Correction ⎛--- I-- high------ ⎞ AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Appendix B Signals and BitsData Terminology Abbreviations and Acronyms AbbreviationsAbbreviation Meaning API AcronymsNMI VGA Related Publications AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet