CY7C1360C
CY7C1362C
TAP DC Electrical Characteristics And Operating Conditions
(0°C < T < +70°C; V | DD | = 3.3V ±0.165V unless otherwise noted)[12] (continued) |
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A |
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Parameter |
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| Description |
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| Conditions |
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| Min. |
| Max. |
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VOL2 |
| Output LOW Voltage |
| IOL = 100 µA |
| VDDQ = 3.3V |
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| 0.2 |
| V | ||||||
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| VDDQ = 2.5V |
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| 0.2 |
| V | ||
VIH |
| Input HIGH Voltage |
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| VDDQ = 3.3V | 2.0 |
| VDD + 0.3 |
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| VDDQ = 2.5V | 1.7 |
| VDD + 0.3 |
| V | ||
VIL |
| Input LOW Voltage |
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| VDDQ = 3.3V |
| 0.7 |
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| VDDQ = 2.5V |
| 0.7 |
| V | |||
IX |
| Input Load Current |
| GND < VIN < VDDQ |
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| 5 |
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Identification Register Definitions |
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Instruction Field |
| CY7C1360C | CY7C1362C |
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| Description |
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| (256KX36) | (512KX18) |
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Revision Number (31:29) |
| 000 |
| 000 | Describes the version number |
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Device Depth (28:24)[13] |
| 01011 | 01011 | Reserved for Internal Use |
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Device Width (23:18) |
| 101000 | 101000 | Defines memory type and architecture |
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Device Width (23:18) 165- FBGA |
| 000000 | 000000 | Defines memory type and architecture |
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Cypress Device ID (17:12) |
| 100110 | 010110 | Defines width and density |
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Cypress JEDEC ID Code (11:1) |
| 00000110100 | 00000110100 | Allows unique identification of SRAM vendor | |||||||||||||
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ID Register Presence Indicator (0) |
| 1 |
| 1 | Indicates the presence of an ID register |
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Scan Register Sizes |
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| Register Name |
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| Bit Size (x36) |
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| Bit Size (x18) |
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Instruction |
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| 3 |
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| 3 |
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Bypass |
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| 1 |
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| 1 |
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ID |
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| 32 |
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| 32 |
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Boundary Scan Order |
| 71 |
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| 71 |
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Boundary Scan Order |
| 71 |
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| 71 |
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Identification Codes
Instruction | Code | Description |
EXTEST | 000 | Captures I/O ring contents. Places the boundary scan register between TDI and TDO. |
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| Forces all SRAM outputs to |
IDCODE | 001 | Loads the ID register with the vendor ID code and places the register between TDI and |
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| TDO. This operation does not affect SRAM operations. |
SAMPLE Z | 010 | Captures I/O ring contents. Places the boundary scan register between TDI and TDO. |
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| Forces all SRAM output drivers to a |
RESERVED | 011 | Do Not Use: This instruction is reserved for future use. |
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SAMPLE/PRELOAD | 100 | Captures I/O ring contents. Places the boundary scan register between TDI and TDO. |
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| Does not affect SRAM operation. |
RESERVED | 101 | Do Not Use: This instruction is reserved for future use. |
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RESERVED | 110 | Do Not Use: This instruction is reserved for future use. |
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BYPASS | 111 | Places the bypass register between TDI and TDO. This operation does not affect SRAM |
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Note: |
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13. Bit #24 is “1” in the Register Definitions for both 2.5V and 3.3V versions of this device.
Document #: | Page 15 of 31 |
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