Switching Waveforms, Read Cycle Timing23

CY7C1360C

CY7C1362C

Switching Waveforms

Read Cycle Timing[23]

tCYC

CLK

tCH

tADS tADH

ADSP

ADSC

tAS tAH

tCL

tADS tADH

ADDRESS

GW, BWE, BWx

A2	A3
tWES tWEH	Burst continued with
tWES tWEH	new base address

ADV

Data Out (Q)

tCES tCEH

	tADVS	tADVH
				ADV
				suspends
				burst.
		tOEV	tCO
	tOEHZ	tOELZ	tDOH
	tCLZ
High-Z	Q(A1)		Q(A2)	Q(A2 + 1)	Q(A2 + 2)	Q(A2 + 3)
	tCO
	Single READ				BURST READ
			DON’T CARE	UNDEFINED

Deselect cycle

tCHZ

Q(A2)

Q(A2 + 1)

Burst wraps around to its initial state

Note:

23. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

Document #: 38-05540 Rev. *H

Page 21 of 31

[+] Feedback

Page 21

Image 21

Cypress CY7C1360C, CY7C1362C manual Switching Waveforms, Read Cycle Timing23

Contents

Logic Block Diagram CY7C1362C 512K x FeaturesFunctional Description1 Cypress Semiconductor Corporation Selection Guide Maximum Access Time Maximum Operating Current250 MHz 200 MHz 166 MHz Unit Maximum Cmos Standby Current Document # 38-05540 Rev. *H Pin Configurations Pin Tqfp Pinout 3 Chip Enables a Version CY7C1360C 256K XCY7C1362C 512K x CY7C1362C Pin Configurations Pin Tqfp Pinout 2 Chip Enables AJ Version NC/576M Pin Configurations Ball BGA Pinout 2 Chip Enables with JtagNC/72M NC/36M NC/288M Pin Configurations Ball Fbga Pinout 3 Chip Enable with Jtag NC/18MNC/72M Pin Definitions Single Write Accesses Initiated by Adsp Single Read AccessesSingle Write Accesses Initiated by Adsc Functional Overview Interleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Read Cycle, Continue Burst Next Partial Truth Table for Read/Write5Write Cycle, Continue Burst Next Read Cycle, Suspend Burst Write Cycle, Suspend Burst Test Access Port TAP Disabling the Jtag FeatureTruth Table for Read/Write5 Ieee 1149.1 Serial Boundary Scan Jtag Performing a TAP Reset TAP Controller Block DiagramTAP Registers TAP Instruction Set Idcode TAP Timing TAP DC Electrical Characteristics And Operating Conditions TAP AC Switching Characteristics Over the Operating Range103V TAP AC Test Conditions 5V TAP AC Test Conditions Identification Register Definitions Scan Register SizesIdentification Codes CY7C1362C 512K x Bit# Ball ID Signal CY7C1360C 256K x Bit# Ball ID SignalBall Fbga Boundary Scan Order Name Ball BGA Boundary Scan Order CY7C1362C 512K x Bit# Ball ID Signal Name Maximum Ratings Electrical Characteristics Over the Operating Range14Operating Range Ambient Range Thermal Resistance Capacitance16AC Test Loads and Waveforms 3V I/O Test Load 250 200 166 Parameter Description Unit Min Switching Characteristics Over the Operating Range 17Min Max Set-up Times Read Cycle Timing23 Switching Waveforms BWE BWX ADV Write Cycle Timing23 CLZ Read/Write Cycle Timing23, 25 DON’T Care ZZ Mode Timing27 Ordering Information CY7C1360C CY7C1362C CY7C1360C CY7C1362C Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package Diagrams 90±0.05 Ball Pbga 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Issue Date Orig. Description of Change