Cypress CY7C1360C, CY7C1362C Write Cycle Timing

CY7C1360C

CY7C1362C

Document #: 38-05540 Rev. *H Page 22 of 31

Write Cycle Timing[23, 24]

Note:

24.Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW.

Switching Waveforms (continued)

tCYC

tCL

CLK

ADSP

tADH

tADS

ADDRESS

tCH

ADSC

tAH

tAS

tCEH

tCES

BWE,

ata Out (Q)

High-Z

ADV

BURST READ BURST WRITE

D(A2) D(A2 + 1) D(A2 + 1)

D(A1) D(A3) D(A3 + 1) D(A3 + 2)D(A2 + 3)

A2 A3

Data In (D)

Extended BURST WRITE

D(A2 + 2)

Single WRITE

tADH

tADS

tADH

tADS

tOEHZ

tADVH

ADVS

tWEH

tWES

tDH

tDS

tWEH

tWES

Byte write signals are

ignored for first cycle when

ADSP initiates burst

ADSC extends burst

ADV suspends burst

DON’T CARE UNDEFINED

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Contents

Main 9-Mbit (256K x 36/512K x 18) Pipelined SRAM CY7C1360C CY7C1362C Features Functional Description Logic Block Diagram CY7C1362C (512K x 18) CY7C1360C CY7C1362C Selection Guide ADDRESS REGISTER A ZZ CY7C1360C CY7C1362C Document #: 38-05540 Rev. *H Page 3 of 31 Pin Configurations CY7C1360C (256K X 36) CY7C1362C (512K x 18) 100-Pin TQFP Pinout (2 Chip Enables) (AJ Version) CY7C1362C (512K x 18) CY7C1360C (256K x 36) 119-Ball BGA Pinout (2 Chip Enables with JTAG) CY7C1360C CY7C1362C 165-Ball FBGA Pinout (3 Chip Enable with JTAG) CY7C1362C (512K x 18) CY7C1360C (256K x 36) 2345671 A B C D E F G H J K L M N P R CY7C1360C CY7C1362C Pin Definitions Functional Overview Pin Definitions Interleaved Burst Address Table (MODE = Floating or VDD) Linear Burst Address Table (MODE = GND) ZZ Mode Electrical Characteristics Truth Table Partial Truth Table for Read/Write Truth Table IEEE 1149.1 Serial Boundary Scan (JTAG) Truth Table for Read/Write TAP Controller Block Diagram S y CY7C1360C CY7C1362C TAP Timing 3.3V TAP AC Test Conditions 3.3V TAP AC Output Load Equivalent F DO T Identification Register Definitions TAP DC Electrical Characteristics And Operating Conditions Scan Register Sizes Identification Codes 165-ball FBGA Boundary Scan Order 119-ball BGA Boundary Scan Order Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance AC Test Loads and Waveforms Switching Characteristics Switching Waveforms Read Cycle Timing Write Cycle Timing Note: 24.Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW. Read/Write Cycle Timing ZZ Mode Timing Page Page Ordering Information Package Diagrams A 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) (51-85050) Package Diagrams 0.900.05 51-85115-*B 0.56 119-Ball PBGA (14 x 22 x 2.4 mm) (51-85115) Package Diagrams 51-85180-*A SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD) 1.40 MAX. 51-85180-*A Document History Page