Capacitance16, Thermal Resistance | Cypress CY7C1360C, CY7C1362C

CY7C1360C

CY7C1362C

Capacitance[16]

	Parameter	Description	Test Conditions	100 TQFP	119 BGA	165 FBGA	Unit
	Parameter	Description	Test Conditions	Max.	Max.	Max.	Unit

	CIN	Input Capacitance	TA = 25°C, f = 1 MHz,	5	5	5	pF
			VDD = 3.3V
	CCLK	Clock Input Capacitance	VDD = 3.3V	5	5	5	pF
			VDDQ = 2.5V
	CI/O	Input/Output Capacitance	VDDQ = 2.5V	5	7	7	pF
	CI/O	Input/Output Capacitance		5	7	7	pF
	Thermal Resistance[16]

	Parameter	Description	Test Conditions	100 TQFP	119 BGA	165 FBGA	Unit
	Parameter	Description	Test Conditions	Package	Package	Package	Unit

	ΘJA	Thermal Resistance	Test conditions follow standard test	29.41	34.1	16.8	°C/W
		(Junction to Ambient)	methods and procedures for
			measuring thermal impedance, per
	ΘJC	Thermal Resistance	measuring thermal impedance, per	6.13	14.0	3	°C/W
	ΘJC	Thermal Resistance	EIA/JESD51.	6.13	14.0	3	°C/W
		(Junction to Case)

AC Test Loads and Waveforms

3.3V I/O Test Load

3.3V

R = 317Ω

OUTPUT

VDDQ

ALL INPUT PULSES

Z0

= 50Ω

OUTPUT

RL

= 50Ω

10%

90%

5 pF

R = 351Ω

GND

INCLUDING

≤ 1 ns

VT = 1.5V

JIG AND

(a)

SCOPE

(b)

(c)

2.5V I/O Test Load

2.5V

R = 1667Ω

OUTPUT

ALL INPUT PULSES

VDDQ

Z0

= 50Ω

OUTPUT

RL

= 50Ω

10%

90%

5 pF

R =1538Ω

GND

INCLUDING

≤ 1 ns

VT = 1.25V

JIG AND

SCOPE

(a)

(b)

(c)

90%

10%

≤ 1 ns

90%

10%

≤ 1 ns

Note:

16. Tested initially and after any design or process change that may affect these parameters.

Document #: 38-05540 Rev. *H

Page 19 of 31

[+] Feedback

Image 19

Cypress CY7C1360C manual Capacitance16, Thermal Resistance, AC Test Loads and Waveforms, 3V I/O Test Load, 5V I/O Test Load

Contents

Cypress Semiconductor Corporation FeaturesLogic Block Diagram CY7C1362C 512K x Functional Description1 Maximum Cmos Standby Current Document # 38-05540 Rev. *H Maximum Access Time Maximum Operating CurrentSelection Guide 250 MHz 200 MHz 166 MHz Unit CY7C1360C 256K X Pin Configurations Pin Tqfp Pinout 3 Chip Enables a VersionCY7C1362C 512K x CY7C1362C Pin Configurations Pin Tqfp Pinout 2 Chip Enables AJ Version NC/288M Pin Configurations Ball BGA Pinout 2 Chip Enables with JtagNC/576M NC/72M NC/36M NC/18M Pin Configurations Ball Fbga Pinout 3 Chip Enable with JtagNC/72M Pin Definitions Functional Overview Single Read AccessesSingle Write Accesses Initiated by Adsp Single Write Accesses Initiated by Adsc Linear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Write Cycle, Suspend Burst Partial Truth Table for Read/Write5Read Cycle, Continue Burst Next Write Cycle, Continue Burst Next Read Cycle, Suspend Burst Ieee 1149.1 Serial Boundary Scan Jtag Disabling the Jtag FeatureTest Access Port TAP Truth Table for Read/Write5 TAP Instruction Set TAP Controller Block DiagramPerforming a TAP Reset TAP Registers Idcode TAP Timing 5V TAP AC Test Conditions TAP AC Switching Characteristics Over the Operating Range10TAP DC Electrical Characteristics And Operating Conditions 3V TAP AC Test Conditions Scan Register Sizes Identification Register DefinitionsIdentification Codes Name CY7C1360C 256K x Bit# Ball ID SignalCY7C1362C 512K x Bit# Ball ID Signal Ball Fbga Boundary Scan Order Ball BGA Boundary Scan Order CY7C1362C 512K x Bit# Ball ID Signal Name Ambient Range Electrical Characteristics Over the Operating Range14Maximum Ratings Operating Range 3V I/O Test Load Capacitance16Thermal Resistance AC Test Loads and Waveforms Set-up Times Switching Characteristics Over the Operating Range 17250 200 166 Parameter Description Unit Min Min Max Read Cycle Timing23 Switching Waveforms BWE BWX ADV Write Cycle Timing23 CLZ Read/Write Cycle Timing23, 25 DON’T Care ZZ Mode Timing27 Ordering Information CY7C1360C CY7C1362C CY7C1360C CY7C1362C Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package Diagrams 90±0.05 Ball Pbga 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Issue Date Orig. Description of Change