Cypress CY7C1360C, CY7C1362C manual Pin Definitions

CY7C1360C

CY7C1362C

Pin Definitions

Name

I/O

Description

A0, A1, A

Input-

Address Inputs used to select one of the address locations. Sampled at the rising edge of

Synchronous

the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3[2]are sampled active. A1, A0

are fed to the two-bit counter..

BW

A,

BW

B

Input-

Byte Write Select Inputs, active LOW. Qualified with

BWE

to conduct Byte Writes to the

BWC, BWD

Synchronous

SRAM. Sampled on the rising edge of CLK.

GW

Input-

Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a

Synchronous

global Write is conducted (ALL bytes are written, regardless of the values on BWX and BWE).

BWE

Input-

Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must

Synchronous

be asserted LOW to conduct a Byte Write.

CLK

Input-

Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the

Clock

burst counter when ADV is asserted LOW, during a burst operation.

CE

1

Input-

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction

Synchronous

with CE

and CE

[2]

to select/deselect the device. ADSP is ignored if CE

is HIGH. CE

1

is

2

3

1

sampled only when a new external address is loaded.

CE2

Input-

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction

Synchronous

with CE

and CE

[2]

to select/deselect the device. CE is sampled only when a new external

1

3

2

address is loaded.

CE

3[2]

Input-

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction

Synchronous

with CE1 and CE2 to select/deselect the device. Not available for AJ package version. Not

connected for BGA. Where referenced,

CE

[2] is assumed active throughout this document for

3

BGA. CE3 is sampled only when a new external address is loaded.

OE

Input-

Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins.

Asynchronous

When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated,

and act as input data pins. OE is masked during the first clock of a read cycle when emerging

from a deselected state.

ADV

Input-

Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it

Synchronous

automatically increments the address in a burst cycle.

ADSP

Input-

Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When

Synchronous

asserted LOW, addresses presented to the device are captured in the address registers. A1,

A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP

is recognized. ASDP is ignored when CE1 is deasserted HIGH.

ADSC

Input-

Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When

Synchronous

asserted LOW, addresses presented to the device are captured in the address registers. A1,

A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP

is recognized.

ZZ

Input-

ZZ “Sleep” Input, active HIGH. When asserted HIGH places the device in a non-time-critical

Asynchronous

“sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or

left floating. ZZ pin has an internal pull-down.

DQs, DQPX

I/O-

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered

Synchronous

by the rising edge of CLK. As outputs, they deliver the data contained in the memory location

specified by the addresses presented during the previous clock rise of the read cycle. The

direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs.

When HIGH, DQs and DQPX are placed in a tri-state condition.

VDD

Power Supply

Power supply inputs to the core of the device.

VSS

Ground

Ground for the core of the device.

VSSQ

I/O Ground

Ground for the I/O circuitry.

VDDQ

I/O Power Supply

Power supply for the I/O circuitry.

MODE

Input-

Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or

Static

left floating selects interleaved burst sequence. This is a strap pin and should remain static

during device operation. Mode pin has an internal pull-up.

TDO

JTAG serial

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG

output

feature is not being utilized, this pin should be disconnected. This pin is not available on TQFP

Synchronous

packages.

Document #: 38-05540 Rev. *H

Page 7 of 31

[+] Feedback