Package Diagrams | Cypress CY7C1362C, CY7C1360C specs

Package Diagrams

CY7C1360C

CY7C1362C

100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) (51-85050)

22.00±0.20

R 0.08 MIN. 0.20 MAX.

0.25

	16.00±0.20
	14.00±0.10
100	81
1	80

0.30±0.08

20.00±0.10

0.65

TYP.

30			51

31			50

0° MIN.

STAND-OFF 0.05 MIN. 0.15 MAX.

12° ±1° (8X)

SEATING PLANE

NOTE:

1.40±0.05

SEE DETAIL

A

0.20 MAX.

1.60 MAX.

0.10

GAUGE PLANE

0° -7°

0.60±0.15

R 0.08 MIN. 0.20 MAX.

1.JEDEC STD REF MS-026

2.BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH

3.DIMENSIONS IN MILLIMETERS

1.00 REF.

0.20 MIN.	51-85050-*B

DETAIL A

Document #: 38-05540 Rev. *H

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Cypress CY7C1362C, CY7C1360C manual Package Diagrams, Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm

Contents

Features Logic Block Diagram CY7C1362C 512K xFunctional Description1 Cypress Semiconductor Corporation Maximum Access Time Maximum Operating Current Selection Guide250 MHz 200 MHz 166 MHz Unit Maximum Cmos Standby Current Document # 38-05540 Rev. *H CY7C1360C 256K X Pin Configurations Pin Tqfp Pinout 3 Chip Enables a VersionCY7C1362C 512K x Pin Configurations Pin Tqfp Pinout 2 Chip Enables AJ Version CY7C1362C Pin Configurations Ball BGA Pinout 2 Chip Enables with Jtag NC/576MNC/72M NC/36M NC/288M NC/18M Pin Configurations Ball Fbga Pinout 3 Chip Enable with JtagNC/72M Pin Definitions Single Read Accesses Single Write Accesses Initiated by AdspSingle Write Accesses Initiated by Adsc Functional Overview Linear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Partial Truth Table for Read/Write5 Read Cycle, Continue Burst NextWrite Cycle, Continue Burst Next Read Cycle, Suspend Burst Write Cycle, Suspend Burst Disabling the Jtag Feature Test Access Port TAPTruth Table for Read/Write5 Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller Block Diagram Performing a TAP ResetTAP Registers TAP Instruction Set TAP Timing Idcode TAP AC Switching Characteristics Over the Operating Range10 TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions 5V TAP AC Test Conditions Scan Register Sizes Identification Register DefinitionsIdentification Codes CY7C1360C 256K x Bit# Ball ID Signal CY7C1362C 512K x Bit# Ball ID SignalBall Fbga Boundary Scan Order Name CY7C1362C 512K x Bit# Ball ID Signal Name Ball BGA Boundary Scan Order Electrical Characteristics Over the Operating Range14 Maximum RatingsOperating Range Ambient Range Capacitance16 Thermal ResistanceAC Test Loads and Waveforms 3V I/O Test Load Switching Characteristics Over the Operating Range 17 250 200 166 Parameter Description Unit MinMin Max Set-up Times Switching Waveforms Read Cycle Timing23 Write Cycle Timing23 BWE BWX ADV Read/Write Cycle Timing23, 25 CLZ ZZ Mode Timing27 DON’T Care Ordering Information CY7C1360C CY7C1362C CY7C1360C CY7C1362C Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Ball Pbga 14 x 22 x 2.4 mm 90±0.05 Soldernotespad Type NON-SOLDER Mask Defined Nsmd Issue Date Orig. Description of Change Document History