CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25
Instruction Register
When the TAP controller is in the
Bypass Register
To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a
Boundary Scan Register
The boundary scan register is connected to all the input and bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the RAM input and output ring when the TAP controller is in the
The boundary scan order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor specific,
TAP Instruction Set
Overview
Eight different instructions are possible with the three bit instruction register. All combinations are listed in Identification Codes on page 15. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below.
Instructions are loaded into the TAP controller during the
To execute the instruction once it is shifted in, the TAP controller needs to be moved into the
EXTEST
The EXTEST instruction enables the preloaded data to be driven out through the system output pins. This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the
IDCODE
The IDCODE instruction causes a vendor specific
The IDCODE instruction is loaded into the instruction register upon power up or whenever the TAP controller is given a test logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the
The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. As there is a large difference in the clock frequencies, it is possible that during the
To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture setup plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register.
Once the data is captured, it is possible to shift out the data by putting the TAP into the
PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells pri- or to the selection of another boundary scan test operation.
Document Number: | Page 12 of 30 |
[+] Feedback