CY7C1386DV25, CY7C1386FV25

CY7C1387DV25, CY7C1387FV25

Switching Characteristics

Over the Operating Range [20, 21]

Parameter

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Description

250 MHz

200 MHz

167 MHz

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Min.

Max.

Min.

Max.

Min.

Max.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tPOWER

 

VDD(Typical) to the first Access [22]

1

 

1

 

1

 

ms

Clock

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tCYC

 

Clock Cycle Time

4.0

 

5.0

 

6.0

 

ns

tCH

 

Clock HIGH

1.7

 

2.0

 

2.2

 

ns

tCL

 

Clock LOW

1.7

 

2.0

 

2.2

 

ns

Output Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tCO

 

Data Output Valid After CLK Rise

 

2.6

 

3.0

 

3.4

ns

tDOH

 

Data Output Hold After CLK Rise

1.0

 

1.3

 

1.3

 

ns

tCLZ

 

Clock to Low-Z [23, 24, 25]

1.0

 

1.3

 

1.3

 

ns

tCHZ

 

Clock to High-Z [23, 24, 25]

 

2.6

 

3.0

 

3.4

ns

tOEV

 

 

 

LOW to Output Valid

 

2.6

 

3.0

 

3.4

ns

OE

tOELZ

 

 

 

LOW to Output Low-Z [23, 24, 25]

0

 

0

 

0

 

ns

OE

tOEHZ

 

 

 

HIGH to Output High-Z [23, 24, 25]

 

2.6

 

3.0

 

3.4

ns

OE

Setup Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tAS

 

Address Setup Before CLK Rise

1.2

 

1.4

 

1.5

 

ns

tADS

 

 

 

 

 

 

 

 

 

 

 

 

 

Setup Before CLK Rise

1.2

 

1.4

 

1.5

 

ns

ADSC,

ADSP

tADVS

 

 

 

 

 

Setup Before CLK Rise

1.2

 

1.4

 

1.5

 

ns

ADV

tWES

 

 

 

 

 

 

 

 

 

 

 

 

 

X Setup Before CLK Rise

1.2

 

1.4

 

1.5

 

ns

GW,

BWE,

BW

tDS

 

Data Input Setup Before CLK Rise

1.2

 

1.4

 

1.5

 

ns

tCES

 

Chip Enable SetUp Before CLK Rise

1.2

 

1.4

 

1.5

 

ns

Hold Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tAH

 

Address Hold After CLK Rise

0.3

 

0.4

 

0.5

 

ns

tADH

 

 

 

 

 

 

 

 

 

 

 

Hold After CLK Rise

0.3

 

0.4

 

0.5

 

ns

ADSP,

ADSC

tADVH

 

 

 

 

Hold After CLK Rise

0.3

 

0.4

 

0.5

 

ns

ADV

tWEH

 

 

 

 

 

 

 

 

 

 

 

 

 

X Hold After CLK Rise

0.3

 

0.4

 

0.5

 

ns

GW,

BWE,

BW

tDH

 

Data Input Hold After CLK Rise

0.3

 

0.4

 

0.5

 

ns

tCEH

 

Chip Enable Hold After CLK Rise

0.3

 

0.4

 

0.5

 

ns

Notes

20.Timing reference level is 1.25V when VDDQ = 2.5V.

21.Test conditions shown in (a) of AC Test Loads unless otherwise noted.

22.This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can be initiated.

23.tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads and Waveforms on page 19. Transition is measured ± 200 mV from steady-state voltage.

24.At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions.

25.This parameter is sampled and not 100% tested.

Document Number: 38-05548 Rev. *E

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Cypress CY7C1387DV25 Switching Characteristics, Parameter Description 250 MHz 200 MHz 167 MHz Unit Min Max, Output Times