CY7C1386DV25, CY7C1386FV25
CY7C1387DV25, CY7C1387FV25
Switching Characteristics
Over the Operating Range [20, 21]
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| Description | 250 MHz | 200 MHz | 167 MHz | Unit | |||
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| Min. | Max. | Min. | Max. | Min. | Max. | |||
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tPOWER |
| VDD(Typical) to the first Access [22] | 1 |
| 1 |
| 1 |
| ms | |||||||||||||
Clock |
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tCYC |
| Clock Cycle Time | 4.0 |
| 5.0 |
| 6.0 |
| ns | |||||||||||||
tCH |
| Clock HIGH | 1.7 |
| 2.0 |
| 2.2 |
| ns | |||||||||||||
tCL |
| Clock LOW | 1.7 |
| 2.0 |
| 2.2 |
| ns | |||||||||||||
Output Times |
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tCO |
| Data Output Valid After CLK Rise |
| 2.6 |
| 3.0 |
| 3.4 | ns | |||||||||||||
tDOH |
| Data Output Hold After CLK Rise | 1.0 |
| 1.3 |
| 1.3 |
| ns | |||||||||||||
tCLZ |
| Clock to | 1.0 |
| 1.3 |
| 1.3 |
| ns | |||||||||||||
tCHZ |
| Clock to |
| 2.6 |
| 3.0 |
| 3.4 | ns | |||||||||||||
tOEV |
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| LOW to Output Valid |
| 2.6 |
| 3.0 |
| 3.4 | ns | |||||||||||
OE | ||||||||||||||||||||||
tOELZ |
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| LOW to Output | 0 |
| 0 |
| 0 |
| ns | |||||||||||
OE | ||||||||||||||||||||||
tOEHZ |
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| HIGH to Output |
| 2.6 |
| 3.0 |
| 3.4 | ns | |||||||||||
OE | ||||||||||||||||||||||
Setup Times |
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tAS |
| Address Setup Before CLK Rise | 1.2 |
| 1.4 |
| 1.5 |
| ns | |||||||||||||
tADS |
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| Setup Before CLK Rise | 1.2 |
| 1.4 |
| 1.5 |
| ns | |
ADSC, | ADSP | |||||||||||||||||||||
tADVS |
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| Setup Before CLK Rise | 1.2 |
| 1.4 |
| 1.5 |
| ns | |||||||||
ADV | ||||||||||||||||||||||
tWES |
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| X Setup Before CLK Rise | 1.2 |
| 1.4 |
| 1.5 |
| ns | |
GW, | BWE, | BW | ||||||||||||||||||||
tDS |
| Data Input Setup Before CLK Rise | 1.2 |
| 1.4 |
| 1.5 |
| ns | |||||||||||||
tCES |
| Chip Enable SetUp Before CLK Rise | 1.2 |
| 1.4 |
| 1.5 |
| ns | |||||||||||||
Hold Times |
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tAH |
| Address Hold After CLK Rise | 0.3 |
| 0.4 |
| 0.5 |
| ns | |||||||||||||
tADH |
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| Hold After CLK Rise | 0.3 |
| 0.4 |
| 0.5 |
| ns | |||
ADSP, | ADSC | |||||||||||||||||||||
tADVH |
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| Hold After CLK Rise | 0.3 |
| 0.4 |
| 0.5 |
| ns | ||||||||||
ADV | ||||||||||||||||||||||
tWEH |
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| X Hold After CLK Rise | 0.3 |
| 0.4 |
| 0.5 |
| ns | |
GW, | BWE, | BW | ||||||||||||||||||||
tDH |
| Data Input Hold After CLK Rise | 0.3 |
| 0.4 |
| 0.5 |
| ns | |||||||||||||
tCEH |
| Chip Enable Hold After CLK Rise | 0.3 |
| 0.4 |
| 0.5 |
| ns |
Notes
20.Timing reference level is 1.25V when VDDQ = 2.5V.
21.Test conditions shown in (a) of AC Test Loads unless otherwise noted.
22.This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can be initiated.
23.tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads and Waveforms on page 19. Transition is measured ± 200 mV from
24.At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
25.This parameter is sampled and not 100% tested.
Document Number: | Page 20 of 30 |
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