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Cypress CY7C1387DV25, CY7C1387FV25, CY7C1386DV25 Ball BGA Boundary Scan Order 14, Bit # Ball ID

Models: CY7C1387FV25 CY7C1386FV25 CY7C1386DV25 CY7C1387DV25

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CY7C1386DV25, CY7C1386FV25

CY7C1387DV25, CY7C1387FV25

119-Ball BGA Boundary Scan Order [14, 15]

Bit #	Ball ID		Bit #	Ball ID		Bit #	Ball ID		Bit #	Ball ID
1	H4		23	F6		45	G4		67	L1

2	T4		24	E7		46	A4		68	M2

3	T5		25	D7		47	G3		69	N1

4	T6		26	H7		48	C3		70	P1

5	R5		27	G6		49	B2		71	K1

6	L5		28	E6		50	B3		72	L2

7	R6		29	D6		51	A3		73	N2

8	U6		30	C7		52	C2		74	P2

9	R7		31	B7		53	A2		75	R3

10	T7		32	C6		54	B1		76	T1

11	P6		33	A6		55	C1		77	R1

12	N7		34	C5		56	D2		78	T2

13	M6		35	B5		57	E1		79	L3

14	L7		36	G5		58	F2		80	R2

15	K6		37	B6		59	G1		81	T3

16	P7		38	D4		60	H2		82	L4

17	N6		39	B4		61	D1		83	N4

18	L6		40	F4		62	E2		84	P4

19	K7		41	M4		63	G2		85	Internal

20	J5		42	A5		64	H1

21	H6		43	K4		65	J3

22	G7		44	E4		66	2K

Notes

14.Balls that are NC (No Connect) are preset LOW.

15.Bit #85 is preset HIGH.

Document Number: 38-05548 Rev. *E

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Cypress CY7C1387DV25, CY7C1387FV25, CY7C1386DV25, CY7C1386FV25 manual Ball BGA Boundary Scan Order 14, Bit # Ball ID

Contents

Features Selection Guide250 MHz 200 MHz 167 MHz Unit Cypress Semiconductor CorporationLogic Block Diagram CY7C1386DV25/CY7C1386FV25 3 512K x Logic Block Diagram CY7C1387DV25/CY7C1387FV25 3 1M xCY7C1386DV25 512K X Pin ConfigurationsCY7C1387DV25 1M x Pin Configurations Ball BGA 1 Chip Enable Pin Configurations Ball Fbga Pinout 3 Chip Enable Power supply inputs to the core of the device Pin DefinitionsName Description Byte write select inputs, active LOW. Qualified withFunctional Overview Interleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDParameter Description Test Conditions Min Max Unit ZZ Mode Electrical CharacteristicsOperation Add. Used Partial Truth Table for Read/Write 5 Truth Table for Read/Write 5Function CY7C1386DV25/CY7C1386FV25 Function CY7C1387DV25/CY7C1387FV25TAP Controller Block Diagram TAP Controller State DiagramIeee 1149.1 Serial Boundary Scan Jtag Instruction Register TAP Instruction SetTAP Timing BypassTAP AC Switching Characteristics TAP AC Test ConditionsTAP AC Output Load Equivalent Parameter Description Min Max Unit ClockIdentification Register Definitions Scan Register SizesIdentification Codes Register Name Bit SizeBall BGA Boundary Scan Order 14 Bit # Ball IDA11 Electrical Characteristics Maximum RatingsOperating Range Range AmbientCapacitance Thermal ResistanceAC Test Loads and Waveforms PackageSwitching Characteristics Setup TimesParameter Description 250 MHz 200 MHz 167 MHz Unit Min Max Output TimesSwitching Waveforms Read Cycle TimingWrite Cycle Timing 26 AdscRead/Write Cycle Timing 26, 28 ZZ Mode Timing 30 DON’T CareOrdering Information CY7C1387DV25-250BZXI Document Number 38-05548 Rev. *E Package Diagrams Pin Plastic Quad Flat pack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Issue Date Orig. Description of Change Document History