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Cypress CY7C1386DV25, CY7C1386FV25, CY7C1387DV25, CY7C1387FV25 Ordering Information

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CY7C1386DV25, CY7C1386FV25

CY7C1387DV25, CY7C1387FV25

Document Number: 38-05548 Rev. *E Page 26 of 30

250 CY7C1386DV25-250AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Commercial

CY7C1387DV25-250AXC

CY7C1386FV25-250BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1387FV25-250BGC

CY7C1386FV25-250BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free

CY7C1387FV25-250BGXC

CY7C1386DV25-250BZC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1387DV25-250BZC

CY7C1386DV25-250BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1387DV25-250BZXC

CY7C1386DV25-250AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Industrial

CY7C1387DV25-250AXI

CY7C1386FV25-250BGI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1387FV25-250BGI

CY7C1386FV25-250BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free

CY7C1387FV25-250BGXI

CY7C1386DV25-250BZI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1387DV25-250BZI

CY7C1386DV25-250BZXI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1387DV25-250BZXI

Ordering Information (continued)

Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or

visit www.cypress.com for actual products offered.

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Contents

Main 18-Mbit (512K x 36/1M x 18) Pipelined DCD Sync SRAM CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Features Functional Description Selection Guide CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Logic Block Diagram CY7C1386DV25/CY7C1386FV25 [3] (512K x 36) E ADSP BW CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Document Number: 38-05548 Rev. *E Page 3 of 30 Pin Configurations CY7C1386DV25 (512K X 36) CY7C1387DV25 (1M x 18) Pin Configurations CY7C1386FV25 (512K x 36) CY7C1387FV25 (1M x 18) 119-Ball BGA (1 Chip Enable) CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Pin Configurations 165-Ball FBGA Pinout CY7C1387DV25 (1M x 18) CY7C1386DV25 (512K x 36) 2345671 A B C D E F G H J K L M N P R CY7C1386DV25, CY7C1386FV25 Pin Definitions CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Functional Overview Pin Definitions CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Interleaved Burst Address Table (MODE = Floating or VDD) Linear Burst Address Table (MODE = GND) ZZ Mode Electrical Characteristics Truth Table Partial Truth Table for Read/Write Truth Table for Read/Write IEEE 1149.1 Serial Boundary Scan (JTAG) TAP Controller State Diagram TAP Controller Block Diagram Page CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 TAP Ti min g TAP AC Test Conditions TAP AC Output Load Equivalent TAP AC Switching Characteristics TAP DC Electrical Characteristics And Operating Conditions Identification Register Definitions Scan Register Sizes Identification Codes 119-Ball BGA Boundary Scan Order[14, 15] 165-Ball BGA Boundary Scan Order Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance AC Test Loads and Waveforms Switching Characteristics Switching Waveforms Read Cycle Timing Write Cycle Timing Read/Write Cycle Timing ZZ Mode Timing CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25 Ordering Information Package Diagrams Figure 1. 100-Pin Plastic Quad Flat pack (14 x 20 x 1.4 mm) (51-85050) A Page Figure 3. 165-Ball FBGA (13 x 15 x 1.4 mm) (51-85180) SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD) 1.40 MAX. 51-85180-*A Package Diagrams NOTES: PACKAGEWEIGHT : 0.475g JEDECREFERENCE : MO-216 / DESIGN 4.6C PACKAGECODE : BB0AC 165 FBGA 13 x 15 x 1.40 MM BB165D/BW165D - NOTES : PACKAGE WEIGHT : 0.475g JEDEC REFERENCE : MO-216 / DESIGN 4.6C PACKAGE CODE : BB0AC Document History Page