Cypress CY7C1387FV25, CY7C1387DV25, CY7C1386DV25, CY7C1386FV25 manual TAP Timing, Bypass

CY7C1386DV25, CY7C1386FV25 CY7C1387DV25, CY7C1387FV25

The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required; that is, while data captured is shifted out, the preloaded data can be shifted in.

BYPASS

When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board.

EXTEST Output Bus Tri-State

IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tri-state mode.

the TAP controller, it will directly control the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it will enable the output buffers to drive the output bus. When LOW, this bit will place the output bus into a High-Z condition.

This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the Shift-DR state. During Update-DR, the value loaded into that shift-register cell will latch into the preload register. When the EXTEST instruction is entered, this bit will directly control the output Q-bus pins. Note that this bit is preset HIGH to enable the output when the device is powered up, and also when the TAP controller is in the Test-Logic-Reset state.

The boundary scan register has a special bit located at bit #85 (for 119-BGA package) or bit #89 (for 165-fBGA package). When this scan cell, called the “extest output bus tri-state,” is latched into the preload register during the Update-DR state in

Reserved

These instructions are not implemented but are reserved for future use. Do not use these instructions.

TAP Timing

1	2
Test Clock
(TCK)	tTH
tTMSS	tTMSH
Test Mode Select
(TMS)
tTDIS	tTDIH
Test Data-In
(TDI)
Test Data-Out
(TDO)

3 4 5 6

tTL tCYC

tTDOV

tTDOX

DON’T CARE

UNDEFINED

Document Number: 38-05548 Rev. *E Page 13 of 30

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