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Cypress CY7C1387FV25, CY7C1387DV25, CY7C1386DV25 manual Switching Waveforms, Read Cycle Timing

Models: CY7C1387FV25 CY7C1386FV25 CY7C1386DV25 CY7C1387DV25

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CY7C1386DV25, CY7C1386FV25

CY7C1387DV25, CY7C1387FV25

Switching Waveforms

Read Cycle Timing [26]

tCYC

CLK

tCH

tADS tADH

tCL

ADSP

tADS tADH

ADSC

tAS tAH

ADDRESS

GW, BWE,BW

ADV

Data Out (DQ)

A1	A2	A3
tWES	tWEH	Burst continued with
tWES	tWEH	new base address
		new base address
tCES tCEH		Deselect
tCES tCEH		cycle
		cycle

tADVS tADVH

ADV suspends burst

		tOEV	tCO
t	tOEHZ	tOELZ	tDOH	tCHZ
	CLZ

High-Z	Q(A1)	Q(A2)	Q(A2 + 1)	Q(A2 + 2)	Q(A2 + 3)	Q(A2)	Q(A2 + 1)	Q(A3)
	tCO					Burst wraps around
						Burst wraps around
	Single READ			BURST READ		to its initial state
	Single READ			BURST READ

DON’T CARE

UNDEFINED

Note

26. On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

Document Number: 38-05548 Rev. *E

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Cypress CY7C1387FV25, CY7C1387DV25, CY7C1386DV25, CY7C1386FV25 manual Switching Waveforms, Read Cycle Timing

Contents

Selection Guide Features250 MHz 200 MHz 167 MHz Unit Cypress Semiconductor Corporation Logic Block Diagram CY7C1387DV25/CY7C1387FV25 3 1M x Logic Block Diagram CY7C1386DV25/CY7C1386FV25 3 512K x Pin Configurations CY7C1386DV25 512K XCY7C1387DV25 1M x Pin Configurations Ball BGA 1 Chip Enable Pin Configurations Ball Fbga Pinout 3 Chip Enable Pin Definitions Power supply inputs to the core of the deviceName Description Byte write select inputs, active LOW. Qualified with Functional Overview Linear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDD ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max UnitOperation Add. Used Truth Table for Read/Write 5 Partial Truth Table for Read/Write 5Function CY7C1386DV25/CY7C1386FV25 Function CY7C1387DV25/CY7C1387FV25 TAP Controller State Diagram TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Instruction Set Instruction Register Bypass TAP Timing TAP AC Test Conditions TAP AC Switching CharacteristicsTAP AC Output Load Equivalent Parameter Description Min Max Unit Clock Scan Register Sizes Identification Register DefinitionsIdentification Codes Register Name Bit Size Bit # Ball ID Ball BGA Boundary Scan Order 14 A11 Maximum Ratings Electrical CharacteristicsOperating Range Range Ambient Thermal Resistance CapacitanceAC Test Loads and Waveforms Package Setup Times Switching CharacteristicsParameter Description 250 MHz 200 MHz 167 MHz Unit Min Max Output Times Read Cycle Timing Switching Waveforms Adsc Write Cycle Timing 26 Read/Write Cycle Timing 26, 28 DON’T Care ZZ Mode Timing 30 Ordering Information CY7C1387DV25-250BZXI Document Number 38-05548 Rev. *E Pin Plastic Quad Flat pack 14 x 20 x 1.4 mm Package Diagrams Ball BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Issue Date Orig. Description of Change