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| CY7C1386DV25, CY7C1386FV25 | ||||
Pin Definitions |
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| CY7C1387DV25, CY7C1387FV25 | |||||||||||||||
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| Name |
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| IO |
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| Description | |||||
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| A0, A1, A |
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| Input- | Address inputs used to select one of the address locations. Sampled at the | ||||||||||||||||
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| Synchronous | rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and | CE | 3 [2] | ||||||
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| are sampled active. A1: A0 are fed to the | ||||||
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| A, |
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| B |
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| Input- | Byte write select inputs, active LOW. Qualified with |
| to conduct byte writes | |||||||
| BW | BW |
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| BWE | ||||||||||||||||
| BWC, BWD | Synchronous | to the SRAM. Sampled on the rising edge of CLK. | ||||||||||||||||||
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| Input- | Global write enable input, active LOW. When asserted LOW on the rising edge | ||||||||
| GW |
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| Synchronous | of CLK, a global write is conducted (all bytes are written, regardless of the values | ||||||||
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| on BWX and BWE). | ||||||
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| Input- | Byte write enable input, active LOW. Sampled on the rising edge of CLK. This | ||||||||
| BWE |
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| Synchronous | signal must be asserted LOW to conduct a byte write. | ||||||||
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| CLK |
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| Input- | Clock input. Used to capture all synchronous inputs to the device. Also used to | ||||||||||||||||
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| Clock | increment the burst counter when ADV is asserted LOW, during a burst operation. | ||||||
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| 1 |
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| Input- | Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in | ||||||||||||
| CE |
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| Synchronous | conjunction with CE2 and CE3 [2] to select or deselect the device. ADSP is ignored | ||||||||
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| if CE1 is HIGH. | CE | 1 is sampled only when a new external address is loaded. | ||||
| CE2 [2] |
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| Input- | Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in | ||||||||||||||||
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| Synchronous | conjunction with CE1 and CE3 [2] to select or deselect the device. CE2 is sampled | ||||||||
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| only when a new external address is loaded. | ||||||
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| 3 [2] |
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| Input- | Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in | |||||||||||||||
| CE |
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| Synchronous | conjunction with CE1 and CE2 to select or deselect the device. Not connected for | ||||||||
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| BGA. Where referenced, CE3 [2] is assumed active throughout this document for | ||||||
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| BGA. CE3 is sampled only when a new external address is loaded. | ||||||
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| Input- | Output enable, asynchronous input, active LOW. Controls the direction of the | |||||||||||
| OE |
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| Asynchronous | IO pins. When LOW, the IO pins behave as outputs. When deasserted HIGH, DQ | ||||||||
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| pins are | ||||||
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| of a read cycle when emerging from a deselected state. | ||||||
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| Input- | Advance input signal, sampled on the rising edge of CLK, active LOW. When | |||||||||
| ADV |
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| Synchronous | asserted, it automatically increments the address in a burst cycle. | ||||||||
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| Input- | Address strobe from processor, sampled on the rising edge of CLK, active | |||||||
| ADSP |
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| Synchronous | LOW. When asserted LOW, addresses presented to the device are captured in the | ||||||||
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| address registers. A1: A0 are also loaded into the burst counter. When ADSP and | ||||||
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| ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is | ||||||
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| deasserted HIGH. | ||||||
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| Input- | Address strobe from controller, sampled on the rising edge of CLK, active | |||||||
| ADSC |
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| Synchronous | LOW. When asserted LOW, addresses presented to the device are captured in the | ||||||||
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| address registers. A1: A0 are also loaded into the burst counter. When ADSP and | ||||||
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| ADSC are both asserted, only ADSP is recognized. | ||||||
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| ZZ |
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| Input- | ZZ sleep input, active HIGH. When asserted HIGH places the device in a | ||||||||||||||||
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| Asynchronous | |||||||||
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| this pin has to be LOW or left floating. ZZ pin has an internal pull down. | ||||||
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| DQs, DQPs |
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| IO- | Bidirectional data IO lines. As inputs, they feed into an | ||||||||||||||||
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| Synchronous | is triggered by the rising edge of CLK. As outputs, they deliver the data contained | ||||||||
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| in the memory location specified by the addresses presented during the previous | ||||||
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| clock rise of the read cycle. The direction of the pins is controlled by OE. When OE | ||||||
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| is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are | ||||||
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| placed in a | ||||||
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| VDD | Power Supply | Power supply inputs to the core of the device. | ||||||||||||||||||
Document Number: |
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| Page 6 of 30 |
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