Manuals / Cypress / Computer Equipment / Computer Hardware

Cypress CY7C1386DV25, CY7C1387DV25, CY7C1387FV25, CY7C1386FV25 manual Write Cycle Timing 26, Adsc

Models: CY7C1387FV25 CY7C1386FV25 CY7C1386DV25 CY7C1387DV25

1 30

Download 30 pages 51.4 Kb

Page 22

CY7C1386DV25, CY7C1386FV25

CY7C1387DV25, CY7C1387FV25

Switching Waveforms (continued)

Write Cycle Timing [26, 27]

t CYC

CLK

tCH tCL

tADS tADH

ADSP

tADS tADH

ADSC

tAS tAH

ADDRESS A1 A2

Byte write signals are ignored for ﬁrst cycle when

ADSP initiates burst

ADSC extends burst

tADS tADH

A3

tWES tWEH

BWE,

BW X

tWES tWEH

GW

	tCES	tCEH
CE
ADV
OE
		t	t
		DS	DH
Data in (D)	High-Z	D(A1)
		tOEHZ
Data Out (Q)

tADVS tADVH

ADV suspends burst

D(A2)

D(A2 + 1)

D(A2 + 3)

D(A3)

D(A3 + 1)

BURST READ

Single WRITE

BURST WRITE

DON’T CARE

Extended BURST WRITE

UNDEFINED

Note

27. Full width write can be initiated by either GW LOW, or by GW HIGH, BWE LOW and BWX LOW.

Document Number: 38-05548 Rev. *E

Page 22 of 30

[+] Feedback

Image 22

Cypress CY7C1386DV25, CY7C1387DV25, CY7C1387FV25, CY7C1386FV25 manual Write Cycle Timing 26, Adsc

Contents

250 MHz 200 MHz 167 MHz Unit FeaturesSelection Guide Cypress Semiconductor Corporation Logic Block Diagram CY7C1386DV25/CY7C1386FV25 3 512K x Logic Block Diagram CY7C1387DV25/CY7C1387FV25 3 1M x CY7C1386DV25 512K X Pin ConfigurationsCY7C1387DV25 1M x Pin Configurations Ball BGA 1 Chip Enable Pin Configurations Ball Fbga Pinout 3 Chip Enable Name Description Power supply inputs to the core of the devicePin Definitions Byte write select inputs, active LOW. Qualified with Functional Overview Interleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GND Parameter Description Test Conditions Min Max Unit ZZ Mode Electrical CharacteristicsOperation Add. Used Function CY7C1386DV25/CY7C1386FV25 Partial Truth Table for Read/Write 5Truth Table for Read/Write 5 Function CY7C1387DV25/CY7C1387FV25 TAP Controller Block Diagram TAP Controller State DiagramIeee 1149.1 Serial Boundary Scan Jtag Instruction Register TAP Instruction Set TAP Timing Bypass TAP AC Output Load Equivalent TAP AC Switching CharacteristicsTAP AC Test Conditions Parameter Description Min Max Unit Clock Identification Codes Identification Register DefinitionsScan Register Sizes Register Name Bit Size Ball BGA Boundary Scan Order 14 Bit # Ball ID A11 Operating Range Electrical CharacteristicsMaximum Ratings Range Ambient AC Test Loads and Waveforms CapacitanceThermal Resistance Package Parameter Description 250 MHz 200 MHz 167 MHz Unit Min Max Switching CharacteristicsSetup Times Output Times Switching Waveforms Read Cycle Timing Write Cycle Timing 26 Adsc Read/Write Cycle Timing 26, 28 ZZ Mode Timing 30 DON’T Care Ordering Information CY7C1387DV25-250BZXI Document Number 38-05548 Rev. *E Package Diagrams Pin Plastic Quad Flat pack 14 x 20 x 1.4 mm Ball BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Issue Date Orig. Description of Change Document History