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Cypress CY7C1386FV25, CY7C1387DV25, CY7C1387FV25, CY7C1386DV25 manual Read/Write Cycle Timing 26, 28

Models: CY7C1387FV25 CY7C1386FV25 CY7C1386DV25 CY7C1387DV25

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CY7C1386DV25, CY7C1386FV25

CY7C1387DV25, CY7C1387FV25

Switching Waveforms (continued)

Read/Write Cycle Timing [26, 28, 29]

tCYC

CLK

tCH tCL

tADS tADH

ADSP

ADSC

tAS tAH

ADDRESS A1

A2

A3

A4

A5

A6

BWE, BW			tWES	tWEH
BWE, BW	X
	tCES	tCEH
CE
ADV
OE
		tCO	tDS	tDH
Data In (D)	High-Z		D(A3)
		t	tOEHZ
		CLZ
Data Out (Q)	High-Z	Q(A1)	Q(A2)
	High-Z	Q(A1)	Q(A2)
	Back-to-Back READs		Single WRITE
			DON’T CARE

tOELZ

D(A5) D(A6)

Q(A4)	Q(A4+3)
BURST READ	Back-to-Back
	WRITEs

UNDEFINED

Notes

28.The data bus (Q) remains in high-Z following a write cycle, unless a new read access is initiated by ADSP or ADSC.

29.GW is HIGH.

Document Number: 38-05548 Rev. *E

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Cypress CY7C1386FV25, CY7C1387DV25, CY7C1387FV25, CY7C1386DV25 manual Read/Write Cycle Timing 26, 28

Contents

Cypress Semiconductor Corporation FeaturesSelection Guide 250 MHz 200 MHz 167 MHz Unit Logic Block Diagram CY7C1387DV25/CY7C1387FV25 3 1M x Logic Block Diagram CY7C1386DV25/CY7C1386FV25 3 512K x CY7C1387DV25 1M x Pin ConfigurationsCY7C1386DV25 512K X Pin Configurations Ball BGA 1 Chip Enable Pin Configurations Ball Fbga Pinout 3 Chip Enable Byte write select inputs, active LOW. Qualified with Power supply inputs to the core of the devicePin Definitions Name Description Functional Overview Linear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDD Operation Add. Used ZZ Mode Electrical CharacteristicsParameter Description Test Conditions Min Max Unit Function CY7C1387DV25/CY7C1387FV25 Partial Truth Table for Read/Write 5Truth Table for Read/Write 5 Function CY7C1386DV25/CY7C1386FV25 Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller State DiagramTAP Controller Block Diagram TAP Instruction Set Instruction Register Bypass TAP Timing Parameter Description Min Max Unit Clock TAP AC Switching CharacteristicsTAP AC Test Conditions TAP AC Output Load Equivalent Register Name Bit Size Identification Register DefinitionsScan Register Sizes Identification Codes Bit # Ball ID Ball BGA Boundary Scan Order 14 A11 Range Ambient Electrical CharacteristicsMaximum Ratings Operating Range Package CapacitanceThermal Resistance AC Test Loads and Waveforms Output Times Switching CharacteristicsSetup Times Parameter Description 250 MHz 200 MHz 167 MHz Unit Min Max Read Cycle Timing Switching Waveforms Adsc Write Cycle Timing 26 Read/Write Cycle Timing 26, 28 DON’T Care ZZ Mode Timing 30 Ordering Information CY7C1387DV25-250BZXI Document Number 38-05548 Rev. *E Pin Plastic Quad Flat pack 14 x 20 x 1.4 mm Package Diagrams Ball BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Issue Date Orig. Description of Change