Cypress CY7C63513C, CY7C63613C, CY7C63413C manual USB Device

CY7C63413C

CY7C63513C

CY7C63613C

The Bus Activity bit is a “sticky” bit that indicates if any non-idle USB event has occurred on the USB bus. The user firmware should check and clear this bit periodically to detect any loss of bus activity. Writing a “0” to the Bus Activity bit clears it while writing a “1” preserves the current value. In other words, the firmware can clear the Bus Activity bit, but only the SIE can set it. The 1.024-ms timer interrupt service routine is normally used to check and clear the Bus Activity bit. The following table shows how the control bits are encoded for this register.

Control	Control Action
Bits
000	Not forcing (SIE controls driver)
001	Force K (D+ HIGH, D– LOW)
010	Force J (D+ LOW, D– HIGH)
011	Force SE0 (D+ LOW, D– LOW)
100	Force SE0 (D− LOW, D+ LOW)
101	Force D− LOW, D+ HiZ
110	Force D− HiZ, D+ LOW
111	Force D− HiZ, D+ HiZ

USB Device

USB Device Address A includes three endpoints: EPA0, EPA1, and EPA2. End Point 0 (EPA0) allows the USB host to recognize, set up, and control the device. In particular, EPA0 is used to receive and transmit control (including set-up) packets.

USB Ports

The USB Controller provides one USB device address with three endpoints. The USB Device Address Register contents

Table 18.USB Device Address Register

are cleared during a reset, setting the USB device address to zero and marking this address as disabled. Figure 18 shows the format of the USB Address Register.

Bit 7 (Device Address Enable) in the USB Device Address Register must be set by firmware before the serial interface engine (SIE) will respond to USB traffic to this address. The Device Address in bits [6:0] must be set by firmware during the USB enumeration process to an address assigned by the USB host that does not equal zero. This register is cleared by a hardware reset or the USB bus reset.

Device Endpoints (3)

The USB controller communicates with the host using dedicated FIFOs, one per endpoint. Each endpoint FIFO is implemented as 8 bytes of dedicated SRAM. There are three endpoints defined for Device “A” that are labeled “EPA0,” “EPA1,” and EPA2.”

All USB devices are required to have an endpoint number 0 (EPA0) that is used to initialize and control the USB device. End Point 0 provides access to the device configuration infor- mation and allows generic USB status and control accesses. End Point 0 is bidirectional as the USB controller can both receive and transmit data.

The endpoint mode registers are cleared during reset. The EPA0 endpoint mode register uses the format shown in Table 19.

Bits[7:5] in the endpoint 0 mode registers (EPA0) are “sticky” status bits that are set by the SIE to report the type of token that was most recently received. The sticky bits must be cleared by firmware as part of the USB processing.

The endpoint mode registers for EPA1 and EPA2 do not use bits [7:5] as shown in Table 20.

Addr:0x10			USB Device Address Register
Device	Device	Device		Device	Device	Device	Device	Device
Address	Address	Address		Address	Address	Address	Address	Address
Enable	Bit 6	Bit 5		Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
R/W	R/W	R/W		R/W	R/W	R/W	R/W	R/W
Table 19.USB Device EPA0, Mode Register
Addr:0x12			USB Device EPA0, Mode Register
Endpoint 0	Endpoint 0	Endpoint 0		Acknowledge	Mode	Mode	Mode	Mode
Set-up	In	Out			Bit 3	Bit 2	Bit 1	Bit 0
Received	Received	Received
R/W	R/W	R/W		R/W	R/W	R/W	R/W	R/W
Table 20.USB Device Endpoint Mode Register
Addr: 0x14, 0x16		USB Device Endpoint Mode Register
Reserved	Reserved	Reserved		Acknowledge	Mode	Mode	Mode	Mode
					Bit 3	Bit 2	Bit 1	Bit 0
R/W	R/W	R/W		R/W	R/W	R/W	R/W	R/W

Document #: 38-08027 Rev. *B Page 16 of 32

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