CY7C63413C

CY7C63513C

CY7C63613C

Table 29.Details of Modes for Differing Traffic Conditions

 

End Point Mode

 

 

 

 

 

 

PID

 

 

 

Set End Point Mode

 

 

3

2

1

0

token

count

buffer

dval

DTOG

DVAL

COUNT

Setup

In

Out

ACK

3

 

2

1

0

 

response

int

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Setup Packet (if accepting)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

See Table 28

Setup

<= 10

data

valid

updates

1

updates

1

UC

UC

1

0

 

0

0

1

 

ACK

yes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

See Table 28

Setup

> 10

junk

x

updates

updates

updates

1

UC

UC

UC

 

NoChange

 

 

ignore

yes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

See Table 28

Setup

x

junk

invalid

updates

0

updates

1

UC

UC

UC

 

NoChange

 

 

ignore

yes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Disabled

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0

0

 

0

x

x

UC

x

UC

UC

UC

UC

UC

UC

UC

 

NoChange

 

 

ignore

no

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Nak In/Out

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0

0

 

1

Out

x

UC

x

UC

UC

UC

UC

UC

1

UC

 

NoChange

 

 

NAK

yes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0

0

 

1

In

x

UC

x

UC

UC

UC

UC

1

UC

UC

 

NoChange

 

 

NAK

yes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Ignore In/Out

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

1

0

 

0

Out

x

UC

x

UC

UC

UC

UC

UC

UC

UC

 

NoChange

 

 

ignore

no

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

1

0

 

0

In

x

UC

x

UC

UC

UC

UC

UC

UC

UC

 

NoChange

 

 

ignore

no

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Stall In/Out

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0

1

 

1

Out

x

UC

x

UC

UC

UC

UC

UC

1

UC

 

NoChange

 

 

Stall

yes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0

1

 

1

In

x

UC

x

UC

UC

UC

UC

1

UC

UC

 

NoChange

 

 

Stall

yes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Control Write

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Normal Out/premature status In

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

0

1

 

1

Out

<= 10

data

valid

updates

1

updates

UC

UC

1

1

1

 

0

1

0

 

ACK

yes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

0

1

 

1

Out

> 10

junk

x

updates

updates

updates

UC

UC

1

UC

 

NoChange

 

 

ignore

yes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

0

1

 

1

Out

x

junk

invalid

updates

0

updates

UC

UC

1

UC

 

NoChange

 

 

ignore

yes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

0

1

 

1

In

x

UC

x

UC

UC

UC

UC

1

UC

1

 

NoChange

 

 

TX 0

yes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NAK Out/premature status In

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

0

1

 

0

Out

<= 10

UC

valid

UC

UC

UC

UC

UC

1

UC

 

NoChange

 

 

NAK

yes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

0

1

 

0

Out

> 10

UC

x

UC

UC

UC

UC

UC

UC

UC

 

NoChange

 

 

ignore

no

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

0

1

 

0

Out

x

UC

invalid

UC

UC

UC

UC

UC

UC

UC

 

NoChange

 

 

ignore

no

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

0

1

 

0

In

x

UC

x

UC

UC

UC

UC

1

UC

1

 

NoChange

 

 

TX 0

yes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Status In/extra Out

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

1

1

 

0

Out

<= 10

UC

valid

UC

UC

UC

UC

UC

1

UC

0

 

0

1

1

 

Stall

yes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

1

1

 

0

Out

> 10

UC

x

UC

UC

UC

UC

UC

UC

UC

 

NoChange

 

 

ignore

no

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

1

1

 

0

Out

x

UC

invalid

UC

UC

UC

UC

UC

UC

UC

 

NoChange

 

 

ignore

no

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

1

1

 

0

In

x

UC

x

UC

UC

UC

UC

1

UC

1

 

NoChange

 

 

TX 0

yes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Control Read

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Normal In/premature status Out

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

1

1

 

1

Out

2

UC

valid

1

1

updates

UC

UC

1

1

 

NoChange

 

 

ACK

yes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

1

1

 

1

Out

2

UC

valid

0

1

updates

UC

UC

1

UC

0

 

0

1

1

 

Stall

yes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

1

1

 

1

Out

!=2

UC

valid

updates

1

updates

UC

UC

1

UC

0

 

0

1

1

 

Stall

yes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

1

1

 

1

Out

> 10

UC

x

UC

UC

UC

UC

UC

UC

UC

 

NoChange

 

 

ignore

no

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

1

1

 

1

Out

x

UC

invalid

UC

UC

UC

UC

UC

UC

UC

 

NoChange

 

 

ignore

no

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

1

1

 

1

In

x

UC

x

UC

UC

UC

UC

1

UC

1

1

 

1

1

0

 

ACK (back)

yes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Nak In/premature status Out

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

1

1

 

0

Out

2

UC

valid

1

1

updates

UC

UC

1

1

 

NoChange

 

 

ACK

yes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

1

1

 

0

Out

2

UC

valid

0

1

updates

UC

UC

1

UC

0

 

0

1

1

 

Stall

yes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

1

1

 

0

Out

!=2

UC

valid

updates

1

updates

UC

UC

1

UC

0

 

0

1

1

 

Stall

yes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

1

1

 

0

Out

> 10

UC

x

UC

UC

UC

UC

UC

UC

UC

 

NoChange

 

 

ignore

no

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

1

1

 

0

Out

x

UC

invalid

UC

UC

UC

UC

UC

UC

UC

 

NoChange

 

 

ignore

no

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

1

1

 

0

In

x

UC

x

UC

UC

UC

UC

1

UC

UC

 

NoChange

 

 

NAK

yes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Status Out/extra In

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0

1

 

0

Out

2

UC

valid

1

1

updates

UC

UC

1

1

 

NoChange

 

 

ACK

yes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0

1

 

0

Out

2

UC

valid

0

1

updates

UC

UC

1

UC

0

 

0

1

1

 

Stall

yes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Document #: 38-08027 Rev. *B

 

 

 

 

 

 

 

 

 

 

 

 

 

Page 23 of 32

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Page 23
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Cypress CY7C63413C, CY7C63613C, CY7C63513C manual Set End Point Mode, Setup Packet if accepting, Control Write, Control Read

CY7C63613C, CY7C63413C, CY7C63513C specifications

The Cypress CY7C63513C, CY7C63413C, and CY7C63613C are versatile programmable logic devices that are part of the Cypress family of microcontrollers designed for diverse applications. These devices are particularly well-suited for embedded systems, consumer electronics, and industrial control systems due to their robust features and technologies.

One of the standout characteristics of these devices is their programmable architecture, which allows for flexible design implementations. The CY7C63513C features 32 programmable I/O pins and an 8-bit microcontroller core, which provides ample resource allocation for various input/output operations. The device supports various communication interfaces, including SPI and I2C, enabling seamless integration into different system configurations.

The CY7C63413C is a highly adaptable component, offering similar features but with an enhanced flexibility in its I/O configuration, making it ideal for applications that require quick prototyping and development cycles. Its extensive instruction set allows for more complex processing tasks, catering to advanced applications in automation and signal processing.

On the other hand, the CY7C63613C provides an advanced level of integration with built-in support for multiple power management modes. This feature is crucial in modern battery-operated devices where energy conservation is a primary concern. Its low-power operation enhances the usability in portable applications while still maintaining performance.

In terms of performance, all three devices boast high-speed operation, with clock frequencies reaching up to 24 MHz. This ensures that they can efficiently handle tasks that require real-time processing, such as sensor data management and control algorithms. The devices are also equipped with an on-chip EEPROM and RAM, allowing for data storage and quick retrieval.

In addition to their performance characteristics, the CY7C63513C, CY7C63413C, and CY7C63613C are designed with reliability in mind. They incorporate robust error detection and correction features, ensuring data integrity during operation. This reliability is essential for critical applications, such as automotive systems and industrial automation.

Overall, the Cypress CY7 series presents an appealing solution for developers looking for a blend of flexibility, performance, and reliability in their embedded designs. Their programmability and support for multiple communication protocols make them a formidable choice in today’s fast-paced technological landscape, paving the way for innovative applications across various industries.