CY7C63413C
CY7C63513C
CY7C63613C
Document #: 38-08027 Rev. *B Page 20 of 32
Interrupt Vectors
The Interrupt Vectors supported by the USB Controller are
listed in Table 27. Although Reset is not an interrupt, per se,
the first instruction executed after a reset is at PROM address
0x0000—which corresponds to the first entry in the Interrupt
Vector Table. Because the JMP instruction is 2 bytes long, the
interrupt vectors occupy 2 bytes.
Interrupt Latency
Interrupt latency can be calculated from the following
equation:
Interrupt Latency =(Number of clock cycles remaining in the
current instruction)
+ (10 clock cycles for the CALL instruction)
+ (5 clock cycles for the JMP instruction)
For example, if a 5 clock cycle instruction such as JC is being
executed when an interrupt occurs, the first instruction of the
Interrupt Service Routine will execute a min. of 16 clocks
(1+10+5) or a max. of 20 clocks (5+10+5) after the interrupt is
issued. Remember that the interrupt latches are sampled at
the rising edge of the last clock cycle in the current instruction.
USB Bus Reset Interrupt
The USB Bus Reset interrupt is asserted when a USB bus
reset condition is detected. A USB bus reset is indicated by a
single ended zero (SE0) on the upstream port for more than 8
microseconds.
Timer Interrupt
There are two timer interrupts: the 128-µs interrupt and the
1.024-ms interrupt. The user should disable both timer inter-
rupts before going into the suspend mode to avoid possible
conflicts between servicing the interrupts first or the suspend
request first.
USB Endpoint Interrupts
There are three USB endpoint interrupts, one per endpoint.
The USB endpoints interrupt after the either the USB host or
the USB controller sends a packet to the USB.
DAC Interrupt
Each DAC I/O pin can generate an interrupt, if enabled.The
interrupt polarity for each DAC I/O pin is programmable. A
positive polarity is a rising edge input while a negative polarity
is a falling edge input. All of the DAC pins share a single
interrupt vector, which means the firmware will need to read
the DAC port to determine which pin or pins caused an
interrupt.
Please note that if one DAC pin triggered an interrupt, no other
DAC pins can cause a DAC interrupt until that pin has returned
to its inactive (non-trigger) state or the corresponding interrupt
enable bit is cleared. The USB Controller does not assign
interrupt priority to different DAC pins and the DAC Interrupt
Enable Register is not cleared during the interrupt
acknowledge process.
GPIO Interrupt
Each of the 32 GPIO pins can generate an interrupt, if enabled.
The interrupt polarity can be programmed for each GPIO port
as part of the GPIO configuration. All of the GPIO pins share
a single interrupt vector, which means the firmware will need
to read the GPIO ports with enabled interrupts to determine
which pin or pins caused an interrupt.
Please note that if one port pin triggered an interrupt, no other
port pins can cause a GPIO interrupt until that port pin has
returned to its inactive (non-trigger) state or its corresponding
port interrupt enable bit is cleared. The USB Controller does
not assign interrupt priority to different port pins and the Port
Interrupt Enable Registers are not cleared during the interrupt
acknowledge process.
Table 27.Interrupt Vector Assignments
Interrupt Vector Number ROM Address Function
not applicable 0x0000 Execution after Reset begins here
10x0002 USB Bus Reset interrupt
20x0004 128-µs timer interrupt
30x0006 1.024-ms timer interrupt
40x0008 USB Address A Endpoint 0 interrupt
50x000A USB Address A Endpoint 1 interrupt
60x000C USB Address A Endpoint 2 interrupt
70x000E Reserved
80x0010 Reserved
90x0012 Reserved
10 0x0014 DAC interrupt
11 0x0016 GPIO interrupt
12 0x0018 Reserved
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