CY7C63413C
CY7C63513C
CY7C63613C
Document #: 38-08027 Rev. *B Page 15 of 32
USB Serial Interface Engine (SIE)The SIE allows the microcontroller to communicate with the
USB host. The SIE simplifies the interface between the micro-
controller and USB by incorporating hardware that handles the
following USB bus activity independently of the microcon-
troller:
• Bit stuffing/unstuffing
• Checksum generation/checking
•ACK/NAK
• Token type identification
• Address checking
Firmware is required to handle the rest of the USB interface
with the following tasks:
• Coordinate enumeration by responding to set-up packets
• Fill and empty the FIFOs
• Suspend/Resume coordination
• Verify and select Data toggle values
USB Enumeration
The enumeration sequence is shown below:
1.The host computer sends a Setup packet followed by a
Data packet to USB address 0 requesting the Device de-
scriptor.
2.The USB Controller decodes the request and retrieves its
Device descriptor from the program memory space.
3.The host computer performs a con trol read sequence and
the USB Controller responds by sending the Device
descriptor over the USB bus.
4.After receiving the descripto r, the host computer sends a
Setup packet followed by a Data packet to address 0
assigning a new USB address to the device.
5.The USB Controller stores the new address in its USB
Device Address Register after the no-data control
sequence is complete.
6.The host sends a request for the Device de scrip tor using
the new USB address.
7.The USB Controll er decodes the request and retrieves the
Device descriptor from the program memory.
8.The host performs a control read seq uence and the USB
Controller responds by sending its Device descriptor over
the USB bus.
9.The host gene rates control reads to the USB Controller to
request the Configuration and Report descriptors.
10.The USB Controller retrieves the descriptors from its
program space and returns the data to the host over the
USB.
PS/2 Operation
PS/2 operation is possible with the CY7C63413C/513C/613C
series through the use of firmware and several operating
modes. The first enabling feature:
1.USB Bus reset on D+ and D− is an interrupt that can be
disabled;
2.USB traffic can be disabled via bit 7 of the USB register;
3.D+ and D− can be monitored and driven via firmware as
independent port bits.
Bits 5 and 4 of the Upstream Status and Control register are
directly connected to the D+ and D− USB pins of the
CY7C63413C/513C/613C. These pins constantly monitor the
levels of these signals with CMOS input thresholds. Firmware
can poll and decode these signals as PS/2 clock and data.
Bits [2:0] defaults to ‘000’ at reset which allows the USB SIE
to control output on D+ and D−. Firmware can override the SIE
and directly control the state of these pins via these 3 control
bits. Since PS/2 is an open drain signaling protocol, these
modes allow all 4 PS/2 states to be generated on the D+ and
D− pins
USB Port Status and Control
USB status and control is regulated by the USB Status and
Control Register located at I/O address 0x1F as shown in
Figure 17. This is a read/write register. All reserved bits must
be written to zero. All bits in the register are cleared during
reset.
Table 17.USB Status and Control Register
Addr:0x1F USB Status and Control Register
76543210
Reserved Reserved D+ D– Bus Activity Control
Bit 2 Control
Bit 1 Control
Bit 0
R R R/W R/W R/W R/W
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