Data Memory Organization

CY7C63413C

CY7C63513C

CY7C63613C

The CY7C63413C/513C/613C microcontrollers provide 256 bytes of data RAM. In normal usage, the SRAM is partitioned

into four areas: program stack, data stack, user variables and USB endpoint FIFOs as shown below:

after reset 8-bit PSP

8-bit DSP

Top of RAM Memory

Address

0x00

user

0xE8

0xF0

0xF8

0xFF

Program Stack begins here and grows upward

Data Stack begins here and grows downward

The user determines the amount of memory required

User Variables

USB FIFO for Address A endpoint 2

USB FIFO for Address A endpoint 1

USB FIFO for Address A endpoint 0

Document #: 38-08027 Rev. *B

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Cypress CY7C63413C, CY7C63613C, CY7C63513C manual Data Memory Organization

CY7C63613C, CY7C63413C, CY7C63513C specifications

The Cypress CY7C63513C, CY7C63413C, and CY7C63613C are versatile programmable logic devices that are part of the Cypress family of microcontrollers designed for diverse applications. These devices are particularly well-suited for embedded systems, consumer electronics, and industrial control systems due to their robust features and technologies.

One of the standout characteristics of these devices is their programmable architecture, which allows for flexible design implementations. The CY7C63513C features 32 programmable I/O pins and an 8-bit microcontroller core, which provides ample resource allocation for various input/output operations. The device supports various communication interfaces, including SPI and I2C, enabling seamless integration into different system configurations.

The CY7C63413C is a highly adaptable component, offering similar features but with an enhanced flexibility in its I/O configuration, making it ideal for applications that require quick prototyping and development cycles. Its extensive instruction set allows for more complex processing tasks, catering to advanced applications in automation and signal processing.

On the other hand, the CY7C63613C provides an advanced level of integration with built-in support for multiple power management modes. This feature is crucial in modern battery-operated devices where energy conservation is a primary concern. Its low-power operation enhances the usability in portable applications while still maintaining performance.

In terms of performance, all three devices boast high-speed operation, with clock frequencies reaching up to 24 MHz. This ensures that they can efficiently handle tasks that require real-time processing, such as sensor data management and control algorithms. The devices are also equipped with an on-chip EEPROM and RAM, allowing for data storage and quick retrieval.

In addition to their performance characteristics, the CY7C63513C, CY7C63413C, and CY7C63613C are designed with reliability in mind. They incorporate robust error detection and correction features, ensuring data integrity during operation. This reliability is essential for critical applications, such as automotive systems and industrial automation.

Overall, the Cypress CY7 series presents an appealing solution for developers looking for a blend of flexibility, performance, and reliability in their embedded designs. Their programmability and support for multiple communication protocols make them a formidable choice in today’s fast-paced technological landscape, paving the way for innovative applications across various industries.

Contents

Cypress Semiconductor Corporation FeaturesFunctional Overview CY7C63413C CY7C63513C CY7C63613C Logic Block Diagram Pin Definitions Programming Model Bit Data Stack Pointer DSP Address ModesMOV A,DSPINIT Buttons EQU 10h MOV A,buttons Instruction Set Summary Operand Opcode Cycles Memory Organization Program Memory OrganizationReserved Program Memory begins here Data Memory Organization Register Summary O Register SummaryRegister Name Address Read/Write Function USB Address A, Endpoint 0 counter register Reset Clocking General Purpose I/O Ports PinAddr Port 1 Data Addr Port 2 Data Port 0 Interrupt Enable Gpio Interrupt Enable PortsGpio Configuration Port Addr Port 0 Interrupt Enable + default Addr Gpio Configuration RegisterDAC Port Cmos Output DAC Port Interrupt Enable Addr DAC Port Interrupt EnableDAC Port Interrupts DAC Isink Registers USB Serial Interface Engine SIE USB Device USB Device Counter Registers Addr 0x11, 0x13 USB Device Counter RegistersData 0/1 Byte count Bit Free-running Timer Timer LSB Timer RegisterAddr Timer Register LSB Timer MSB Timer Register Addr Timer Register MSB Global Interrupt Enable Register Addr USB End Point Interrupt Enable Register AddrInterrupts Gpio DAC Interrupt Vectors Interrupt Vector AssignmentsInterrupt Vector Number ROM Address Function Interrupt Latency USB Register Mode Encoding Truth TablesEncoding NAK What the SIE does to Mode bits PID Status bits Interrupt? Encoding Set End Point Mode Setup Packet if acceptingControl Write Control Read Out endpoint Power-On Reset Absolute Maximum RatingsParameter Min Max Unit Conditions General USB Interface Switching Characteristics Differential Data Lines Ordering Information Ordering CodePackage Package Type Operating Size Range Die Pad Locations DIe Pad Locations in microns Pad # Pin Name Lead 600-Mil Molded DIP P2 Package DiagramsLead Shrunk Small Outline Package SP48 Package Diagrams Lead 300-Mil Soic S24.3/SZ24.3 PIN 1 ID Issue Orig. Description of Change Date Document HistoryDSG TYJ