CY7C63413C
CY7C63513C
CY7C63613C
Document #: 38-08027 Rev. *B Page 18 of 32
12-bit Free-running Timer
The 12-bit timer provides two interrupts (128 µs and 1.024 ms)
and allows the firmware to directly time events that are up to
4 ms in duration. The lower 8 bits of the timer can be read
directly by the firmware. Reading the lower 8 bits latches the
upper 4 bits into a temporary register. When the firmware
reads the upper 4 bits of the timer, it is actually reading the
count stored in the temporary register. The effect of this logic
is to ensure a stable 12-bit timer value can be read, even when
the two reads are separated in time.
Timer (LSB)
Timer (MSB)
Processor Status and Control Register
The “Run” (bit 0) is manipulated by the HALT instruction. When
Halt is executed, the processor clears the run bit and halts at
the end of the current instruction. The processor remains
halted until a reset (Power On or Watch Dog). Notice, when
writing to the processor status and control register, the run bit
should always be written as a “1.”
Table 22.Timer Register
Addr: 0x24 Timer Register (LSB)
Timer
Bit 7 Timer
Bit 6 Timer
Bit 5 Timer
Bit 4 Timer
Bit 3 Timer
Bit 2 Timer
Bit 1 Timer
Bit 0
R R R R R R R R
Table 23.Timer Register
Addr: 0x25 Timer Register (MSB)
Reserved Reserved Reserved Reserved Timer
Bit 11 Timer
Bit 10 Timer
Bit 9 Timer
Bit 8
R R R R
Figure 6. Timer Block Diagram
10 9 785
6432 1-MHz clock

1.024-ms interrupt

128-µs interrupt

To Timer Register

8

1 011
L1 L0L2L3
D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Table 24.Processor Status and Control Register
Addr: 0xFF Processor Status and Control Register POR Default: 0x0101
WDC Reset: 0x41
7 6 5 4 3 2 1 0
IRQ
Pending Watch Dog
Reset USB Bus
Reset Power-on
Reset Suspend, Wait
for Interrupt Interrupt
Mask Single Step Run
RR/W R/W R/W R/W R R/W R/W
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