CY7C63413C
CY7C63513C
CY7C63613C
Document #: 38-08027 Rev. *B Page 22 of 32
The response of the SIE can be summarized as follows:
1.the SIE will only respond to valid transactions, and will ig-
nore non-valid ones;
2.the SIE will generate IRQ when a valid transaction is
completed or when the DMA buffer is corrupted
3.an incoming Data packet is valid if the count is <= 10 (CRC
inclusive) and passes all error checking;
4.a Setup will be ignored by all non-Control endpoints (in
appropriate modes);
5.an In will be i gnored by an Out configured endpoint and vice
versa.
The In and Out PID status is updated at the end of a trans-
action.
The Setup PID status is updated at the beginning of the Data
packet phase.
The entire EndPoint 0 mode and the Count register are locked
to CPU writes at the end of any transaction in which an ACK
is transferred. These registers are only unlocked upon a CPU
read of these registers, and only if that read happens after the
transaction completes. This represents about a 1-µs window
to which to the CPU is locked from register writes to these USB
registers. Normally the firmware does a register read at the
beginning of the ISR to unlock and get the mode register infor-
mation. The interlock on the Mode and Count registers
ensures that the firmware recognizes the changes that the SIE
might have made during the previous transaction.
Figure 7. Decode table forTable 29: “Details of Modes for Differing Traffic Conditions”
Properties of incoming packet
Encoding Status bits What the SIE does to Mode bits
PID Status bits Interrupt?
End Point
Mode End Point
Mode
3
2 1 0 Token count buffer dval DTOG DVAL COUNT Set-
up In Out ACK 3 210Re-
sponse In
t
Setup
In
Out
The validity of the received data
The quality status of the DMA buffer
The number of received bytes Acknowledge phase completed
Legend: UC: unchanged TX: transmit TX0: transmit 0-length packet
x: don’t care RX: receive
available for Control endpoint only
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