Cypress CY7C63513C, CY7C63613C, CY7C63413C manual Pin Definitions, Programming Model

							CY7C63413C
							CY7C63513C
							CY7C63613C
Pin Definitions
		CY7C63413C			CY7C63513C	CY7C63613C
Name	I/O	40-Pin	48-Pin	Die	48-Pin	24-Pin	Description
D+, D–	I/O	1,2	1,2	1,2	1,2	1,2	USB differential data; PS/2 clock and
							data signals
P0[7:0]	I/O	15,26,16	17,32,18	17,32,18,	17,32,18,31,	7, 18, 8, 17, 9,	GPIO port 0 capable of sinking 7 mA
		25,17,24	31,19,30	31,19,30,	19,30,20,29	16, 10, 15	(typical)
		18,23	20,29	20,29
P1[3:0]	I/O	11,30,12,	11,38,12,	11,38,12,	11,38,12,37,	5, 20, 6, 19	GPIO Port 1 capable of sinking 7 mA
		29,13,28,	37,13,36,	37,13,36,	13,36,14,35		(typical).
		14,27	14,35	14,35
P2	I/O	7,34,8,	7,42,8,	7,42,8,	7,42,8,41,9,	n/a	GPIO Port 2 capable of sinking 7 mA
		33,9,32,	41,9,40,	41,9,40,	40,10,39		(typical).
		10,31	10,39	10,39
P3[7:4]	I/O	3,38,4,	3,46,4,	3,46,4,	3,46,4,45,5,	3, 22, 4, 21	GPIO Port 3 capable of sinking 12 mA
		37,5,36,	45,5,44,	45,5,44,	44,6,43		(typical).
		6,35	6,43	6,43
DAC	I/O	n/a	n/a	15,34,16,	15,34,16,33,	n/a	DAC I/O Port with programmable
				33,21,28,	21,28,22,27		current sink outputs. DAC[1:0] offer a
				22,27			programmable range of 3.2 to 16 mA
							typical. DAC[7:2] have a program-
							mable sink current range of 0.2 to 1.0
							mA typical. DAC I/O Port not bonded
							out on CY7C63613C. See note on
							page 12 for firmware code needed for
							unused pins.
XTALIN	IN	21	25	25	25	13	6-MHz ceramic resonator or external
							clock input
XTALOUT	OUT	22	26	26	26	14	6-MHz ceramic resonator
VPP		19	23	23	23	11	Programming voltage supply, ground
							during operation
VCC		40	48	48	48	24	Voltage supply
Vss		20,39	24,47	24,47	24,47	12, 23	Ground

Programming Model

14-bit Program Counter (PC)

The 14-bit Program Counter (PC) allows access for up to 8 kilobytes of EPROM using the CY7C63413C/513C/613C architecture. The program counter is cleared during reset, such that the first instruction executed after a reset is at address 0x0000. This is typically a jump instruction to a reset handler that initializes the application.

The lower eight bits of the program counter are incremented as instructions are loaded and executed. The upper six bits of the program counter are incremented by executing an XPAGE instruction. As a result, the last instruction executed within a 256-byte “page” of sequential code should be an XPAGE instruction. The assembler directive “XPAGEON” will cause the assembler to insert XPAGE instructions automatically. As instructions can be either one or two bytes long, the assembler may occasionally need to insert a NOP followed by an XPAGE for correct execution.

The program counter of the next instruction to be executed, carry flag, and zero flag are saved as two bytes on the program stack during an interrupt acknowledge or a CALL instruction. The program counter, carry flag, and zero flag are restored from the program stack only during a RETI instruction.

Please note the program counter cannot be accessed directly by the firmware. The program stack can be examined by reading SRAM from location 0x00 and up.

8-bit Accumulator (A)

The accumulator is the general purpose, do everything register in the architecture where results are usually calcu- lated.

8-bit Index Register (X)

The index register “X” is available to the firmware as an auxiliary accumulator. The X register also allows the processor to perform indexed operations by loading an index value into X.

8-bit Program Stack Pointer (PSP)

During a reset, the Program Stack Pointer (PSP) is set to zero. This means the program “stack” starts at RAM address 0x00 and “grows” upward from there. Note the program stack pointer is directly addressable under firmware control, using the MOV PSP,A instruction. The PSP supports interrupt service under hardware control and CALL, RET, and RETI instructions under firmware control.

Document #: 38-08027 Rev. *B Page 4 of 32

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