Logic Block Diagram | Cypress CY7C63613C, CY7C63513C, CY7C63413C

CY7C63413C

CY7C63513C

CY7C63613C

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Logic Block Diagram

Pin Configuration

6-MHz ceramic resonator

CY7C63513C	CY7C63413C
48-pin SSOP	48-pin SSOP

OSC

12 MHz 6 MHz

12-MHz

USB

D+ USB

8-bit

Transceiver

PS/2

CPU

D– PORT

EPROM

USB

4/6/8 Kbyte

Bus

SIE

RAM

Interrupt

bit-8

256 byte

Controller

See Note 1

D+		1	48
D+		1	48
D–		2	47
P3[7]		3	46
P3[5]		4	45
P3[3]		5	44
P3[1]		6	43
P3[1]		6	43
P2[7]		7	42
P2[5]		8	41
P2[3]		9	40
P2[1]		10	39
P1[7]		11	38
P1[5]		12	37
P1[3]		13	36
P1[3]		13	36
P1[1]		14	35
DAC[7]		15	34
DAC[5]		16	33
P0[7]		17	32
P0[5]		18	31
P0[3]		19	30
P0[3]		19	30
P0[1]		20	29
DAC[3]		21	28
DAC[1]		22	27
VPP		23	26
Vss		24	25

CY7C63413C 40-pin PDIP

VCC	D+		1	48	VCC
VCC	D+		1	48	VCC
Vss	D–		2	47	Vss
P3[6]	P3[7]		3	46	P3[6]
P3[4]	P3[5]		4	45	P3[4]
P3[2]	P3[3]		5	44	P3[2]
P3[2]	P3[3]		5	44	P3[2]
P3[0]	P3[1]		6	43	P3[0]
P2[6]	P2[7]		7	42	P2[6]
P2[4]	P2[5]		8	41	P2[4]
P2[2]	P2[3]		9	40	P2[2]
P2[0]	P2[1]		10	39	P2[0]
P1[6]	P1[7]		11	38	P1[6]
P1[4]	P1[5]		12	37	P1[4]
P1[2]	P1[3]		13	36	P1[2]
P1[0]	P1[1]		14	35	P1[0]
DAC[6]	NC		15	34	NC
DAC[4]	NC		16	33	NC
P0[6]	P0[7]		17	32	P0[6]
P0[4]	P0[5]		18	31	P0[4]
P0[2]	P0[3]		19	30	P0[2]
P0[0]	P0[1]		20	29	P0[0]
DAC[2]	NC		21	28	NC
DAC[0]	NC		22	27	NC
XTALOUT	VPP		23	26	XTALOUT
XTALIN	Vss		24	25	XTALIN
XTALIN	Vss		24	25	XTALIN

CY7C63613C 24-pin SOIC

12-bit Timer

Watch Dog

Timer

Power-on

Reset

GPIO

P0[0]

D+

1

40

VCC

D+

1

24

VCC

PORT 0

P0[7]

D–

2

39

VSS

D–

2

23

VSS

P3[7]

3

38

P3[6]

P3[7]

3

22

P3[6]

P3[5]

4

37

P3[4]

P3[5]

4

21

P3[4]

P3[3]

5

36

P3[2]

P1[3]

5

20

P1[2]

P1[0]

P3[1]

6

35

P3[0]

P1[1]

6

19

P1[0]

GPIO

P2[7]

7

34

P2[6]

P0[7]

7

18

P0[6]

P2[5]

8

33

P2[4]

P0[5]

8

17

P0[4]

PORT 1

P1[7]

P2[3]

9

32

P2[2]

P0[3]

9

16

P0[2]

P2[1]

10

31

P2[0]

P0[1]

10

15

P0[0]

P1[7]

11

30

P1[6]

VPP

11

14

XTALOUT

P1[5]

12

29

P1[4]

Vss

12

13

XTALIN

P2[0]

P1[3]

13

28

P1[2]

GPIO

P1[1]

14

27

P1[0]

PORT 2

P2[7]

P0[7]

15

26

P0[6]

P0[5]

16

25

P0[4]

CY7C63413C

P0[3]

17

24

P0[2]

P0[1]

18

23

P0[0]

48-Pad Die

GPIO

P3[0]

VPP

19

22

XTALOUT

P3[5] P3[7] D–

CC

High Current

Vss

20

21

XTALIN

P3[3]

D+ V Vss P3[6] P3[4]

PORT 3

Outputs

P3[7]

P3[1]

P2[7]

P3[2]

P2[5]

P3[0]

P2[3]

P2[6]

P2[4]

DAC[0]

P2[1]

P2[2]

DAC

P1[7]

P2[0]

CY7C63513C only

P1[5]

P1[6]

PORT

P1[3]

DAC[7]

P1[4]

P1[1]

P1[2]

DAC[7]

P1[0]

DAC[5]

DAC[6]

DAC[4]

0

P0[7]

P0[6]

P0[5]

P0[4]

P0[3] P0[1]

DAC[3]

PP

IN OUT

DAC[0] DAC[2]

DAC[1] V

Vss XTAL XTAL

P0[0]

P0[2]

0

Note:

1.CY7C63613C is not bonded out for all GPIO pins shown in Logic Block Diagram. Refer to pin configuration diagram for bonded out pins. See note on page 12 for firmware code needed for unused GPIO pins.

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Document #: 38-08027 Rev. *B

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Cypress CY7C63613C, CY7C63513C, CY7C63413C manual Logic Block Diagram

CY7C63613C, CY7C63413C, CY7C63513C specifications

The Cypress CY7C63513C, CY7C63413C, and CY7C63613C are versatile programmable logic devices that are part of the Cypress family of microcontrollers designed for diverse applications. These devices are particularly well-suited for embedded systems, consumer electronics, and industrial control systems due to their robust features and technologies.

One of the standout characteristics of these devices is their programmable architecture, which allows for flexible design implementations. The CY7C63513C features 32 programmable I/O pins and an 8-bit microcontroller core, which provides ample resource allocation for various input/output operations. The device supports various communication interfaces, including SPI and I2C, enabling seamless integration into different system configurations.

The CY7C63413C is a highly adaptable component, offering similar features but with an enhanced flexibility in its I/O configuration, making it ideal for applications that require quick prototyping and development cycles. Its extensive instruction set allows for more complex processing tasks, catering to advanced applications in automation and signal processing.

On the other hand, the CY7C63613C provides an advanced level of integration with built-in support for multiple power management modes. This feature is crucial in modern battery-operated devices where energy conservation is a primary concern. Its low-power operation enhances the usability in portable applications while still maintaining performance.

In terms of performance, all three devices boast high-speed operation, with clock frequencies reaching up to 24 MHz. This ensures that they can efficiently handle tasks that require real-time processing, such as sensor data management and control algorithms. The devices are also equipped with an on-chip EEPROM and RAM, allowing for data storage and quick retrieval.

In addition to their performance characteristics, the CY7C63513C, CY7C63413C, and CY7C63613C are designed with reliability in mind. They incorporate robust error detection and correction features, ensuring data integrity during operation. This reliability is essential for critical applications, such as automotive systems and industrial automation.

Overall, the Cypress CY7 series presents an appealing solution for developers looking for a blend of flexibility, performance, and reliability in their embedded designs. Their programmability and support for multiple communication protocols make them a formidable choice in today’s fast-paced technological landscape, paving the way for innovative applications across various industries.

Contents

Features Functional OverviewCypress Semiconductor Corporation CY7C63413C CY7C63513C CY7C63613C Logic Block Diagram Programming Model Pin Definitions Buttons EQU 10h MOV A,buttons Bit Data Stack Pointer DSPAddress Modes MOV A,DSPINIT Operand Opcode Cycles Instruction Set Summary Program Memory begins here Memory OrganizationProgram Memory Organization Reserved Data Memory Organization USB Address A, Endpoint 0 counter register Register SummaryO Register Summary Register Name Address Read/Write Function Clocking Reset Addr Port 2 Data General Purpose I/O PortsPin Addr Port 1 Data Addr Port 0 Interrupt Enable Port 0 Interrupt EnableGpio Interrupt Enable Ports Gpio Configuration Port Cmos Output + defaultAddr Gpio Configuration Register DAC Port DAC Isink Registers DAC Port Interrupt EnableAddr DAC Port Interrupt Enable DAC Port Interrupts USB Serial Interface Engine SIE USB Device Byte count USB Device Counter RegistersAddr 0x11, 0x13 USB Device Counter Registers Data 0/1 Timer MSB Timer Register Addr Timer Register MSB Bit Free-running TimerTimer LSB Timer Register Addr Timer Register LSB Gpio DAC Global Interrupt Enable Register AddrUSB End Point Interrupt Enable Register Addr Interrupts Interrupt Latency Interrupt VectorsInterrupt Vector Assignments Interrupt Vector Number ROM Address Function NAK USB Register Mode EncodingTruth Tables Encoding Encoding What the SIE does to Mode bits PID Status bits Interrupt? Control Read Set End Point ModeSetup Packet if accepting Control Write Out endpoint USB Interface Power-On ResetAbsolute Maximum Ratings Parameter Min Max Unit Conditions General Switching Characteristics Differential Data Lines Range Ordering InformationOrdering Code Package Package Type Operating Size DIe Pad Locations in microns Pad # Pin Name Die Pad Locations Package Diagrams Lead Shrunk Small Outline Package SP48Lead 600-Mil Molded DIP P2 PIN 1 ID Package Diagrams Lead 300-Mil Soic S24.3/SZ24.3 TYJ Issue Orig. Description of Change DateDocument History DSG