Cypress CY7C63513C, CY7C63613C DAC Port, Cmos Output, + default, Addr Gpio Configuration Register

CY7C63413C

CY7C63513C

CY7C63613C

Table 11.Possible Port Configurations

Port Configuration bits	Pin Interrupt Bit	Driver Mode	Interrupt Polarity
11	X	Resistive	-
10	0	CMOS Output	disabled
10	1	Open Drain	disabled
01	X	Open Drain	-
00	X	Open Drain	+ (default)

In “Resistive” mode, a 7-kΩpull-up resistor is conditionally enabled for all pins of a GPIO port. The resistor is enabled for any pin that has been written as a “1.” The resistor is disabled on any pin that has been written as a “0.” An I/O pin will be driven high through a 7-kΩpull-up resistor when a “1” has been written to the pin. Or the output pin will be driven LOW, with the pull-up disabled, when a “0” has been written to the pin. An I/O pin that has been written as a “1” can be used as an input pin with an integrated 7-kΩpull-up resistor. Resistive mode selects a negative (falling edge) interrupt polarity on all pins that have the GPIO interrupt enabled.

In “CMOS” mode, all pins of the GPIO port are outputs that are actively driven. The current source and sink capacity are roughly the same (symmetric output drive). A CMOS port is not a possible source for interrupts.

A port configured in CMOS mode has interrupt generation disabled, yet the interrupt mask bits serve to control port

direction. If a port’s associated Interrupt Mask bits are cleared, those port bits are strictly outputs. If the Interrupt Mask bits are set then those bits will be open drain inputs. As open drain inputs, if their data output values are ‘1’ those port pins will be CMOS inputs (HIGH Z output).

In “Open Drain” mode the internal pull-up resistor and CMOS driver (HIGH) are both disabled. An I/O pin that has been written as a “1” can be used as either a high-impedance input or a three-state output. An I/O pin that has been written as a “0” will drive the output LOW. The interrupt polarity for an open drain GPIO port can be selected as either positive (rising edge) or negative (falling edge).

During reset, all of the bits in the GPIO Configuration Register are written with “0.” This selects the default configuration: Open Drain output, positive interrupt polarity for all GPIO ports.

Addr: 0x08			GPIO Configuration Register
7	6	5	4	3	2	1	0
Port 3	Port 3	Port 2	Port 2	Port 1	Port 1	Port 0	Port 0
Config Bit 1	Config Bit 0	Config Bit 1	Config Bit 0	Config Bit 1	Config Bit 0	Config Bit 1	Config Bit 0
W	W	W	W	W	W	W	W

Table 12.GPIO Configuration Register

DAC Port

VCC

Internal		Data
Data Bus		Out
		Latch
	DAC Write

Internal

Buffer

DAC Read

Interrupt

Enable

Interrupt

Polarity

Isink Register

Interrupt Logic

Q1

14 KΩ

4 bits Isink	ESD
DAC

to Interrupt Controller

DAC

I/O Pin

Figure 5. Block Diagram of DAC Port

Document #: 38-08027 Rev. *B Page 13 of 32

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