CY7C63413C

CY7C63513C

CY7C63613C

The ‘Acknowledge’ bit is set whenever the SIE engages in a transaction that completes with an ‘ACK’ packet.

The ‘set-up’ PID status (bit[7]) is forced HIGH from the start of the data packet phase of the set-up transaction, until the start of the ACK packet returned by the SIE. The CPU is prevented from clearing this bit during this interval, and subsequently until the CPU first does an IORD to this endpoint 0 mode register.

Bits[6:0] of the endpoint 0 mode register are locked from CPU IOWR operations only if the SIE has updated one of these bits, which the SIE does only at the end of a packet transaction (set- up... Data... ACK, or Out... Data... ACK, or In... Data... ACK). The CPU can unlock these bits by doing a subsequent I/O read of this register.

Firmware must do an IORD after an IOWR to an endpoint 0 register to verify that the contents have changed and that the SIE has not updated these values.

Table 21.USB Device Counter Registers

While the ‘set-up’ bit is set, the CPU cannot write to the DMA buffers at memory locations 0xE0 through 0xE7 and 0xF8 through 0xFF. This prevents an incoming set-up transaction from conflicting with a previous In data buffer filling operation by firmware.

The mode bits (bits [3:0]) in an Endpoint Mode Register control how the endpoint responds to USB bus traffic. The mode bit encoding is shown in Section .

The format of the endpoint Device counter registers is shown in Table 21.

Bits 0 to 3 indicate the number of data bytes to be transmitted during an IN packet, valid values are 0 to 8 inclusive. Data Valid bit 6 is used for OUT and set-up tokens only. Data 0/1 Toggle bit 7 selects the DATA packet’s toggle state: 0 for DATA0, 1 for DATA1.

Addr: 0x11, 0x13, 0x15

 

USB Device Counter Registers

 

 

 

 

 

 

 

 

 

 

 

 

 

Data 0/1

Data Valid

Reserved

 

Reserved

Byte count

 

Byte count

Byte count

Byte count

Toggle

 

 

 

 

Bit 3

 

Bit 2

Bit 1

Bit 0

 

 

 

 

 

 

 

 

 

 

R/W

R/W

R/W

 

R/W

R/W

 

R/W

R/W

R/W

 

 

 

 

 

 

 

 

 

 

Document #: 38-08027 Rev. *B

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Cypress CY7C63413C, CY7C63613C, CY7C63513C manual Addr 0x11, 0x13 USB Device Counter Registers, Data 0/1, Byte count
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CY7C63613C, CY7C63413C, CY7C63513C specifications

The Cypress CY7C63513C, CY7C63413C, and CY7C63613C are versatile programmable logic devices that are part of the Cypress family of microcontrollers designed for diverse applications. These devices are particularly well-suited for embedded systems, consumer electronics, and industrial control systems due to their robust features and technologies.

One of the standout characteristics of these devices is their programmable architecture, which allows for flexible design implementations. The CY7C63513C features 32 programmable I/O pins and an 8-bit microcontroller core, which provides ample resource allocation for various input/output operations. The device supports various communication interfaces, including SPI and I2C, enabling seamless integration into different system configurations.

The CY7C63413C is a highly adaptable component, offering similar features but with an enhanced flexibility in its I/O configuration, making it ideal for applications that require quick prototyping and development cycles. Its extensive instruction set allows for more complex processing tasks, catering to advanced applications in automation and signal processing.

On the other hand, the CY7C63613C provides an advanced level of integration with built-in support for multiple power management modes. This feature is crucial in modern battery-operated devices where energy conservation is a primary concern. Its low-power operation enhances the usability in portable applications while still maintaining performance.

In terms of performance, all three devices boast high-speed operation, with clock frequencies reaching up to 24 MHz. This ensures that they can efficiently handle tasks that require real-time processing, such as sensor data management and control algorithms. The devices are also equipped with an on-chip EEPROM and RAM, allowing for data storage and quick retrieval.

In addition to their performance characteristics, the CY7C63513C, CY7C63413C, and CY7C63613C are designed with reliability in mind. They incorporate robust error detection and correction features, ensuring data integrity during operation. This reliability is essential for critical applications, such as automotive systems and industrial automation.

Overall, the Cypress CY7 series presents an appealing solution for developers looking for a blend of flexibility, performance, and reliability in their embedded designs. Their programmability and support for multiple communication protocols make them a formidable choice in today’s fast-paced technological landscape, paving the way for innovative applications across various industries.
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