Cypress CY7C63413C, CY7C63513C, CY7C63613C Interrupts

CY7C63413C

CY7C63513C

CY7C63613C

Document #: 38-08027 Rev. *B Page 19 of 32

The “Single Step” (bit 1) is provided to support a hardware

debugger. When single step is set, the processor will execute

one instruction and halt (clear the run bit). This bit must be

cleared for normal operation.

The “Interrupt Mask” (bit 2) shows whether interrupts are

enabled or disabled. The firmware has no direct control over

this bit as writing a zero or one to this bit position will have no

effect on interrupts. Instructions DI, EI, and RETI manipulate

the internal hardware that controls the state of the interrupt

mask bit in the Processor Status and Control Register.

Writing a “1” to “Suspend, Wait for Interrupts” (bit 3) will halt

the processor and cause the microcontroller to enter the

“suspend” mode that significantly reduces power

consumption. A pending interrupt or bus activity will cause the

device to come out of suspend. After coming out of suspend,

the device will resume firmware execution at the instruction

following the IOWR which put the part into suspend. An IOWR

that attempts to put the part into suspend will be ignored if

either bus activity or an interrupt is pending.

The “Power-on Reset” (bit 4) is only set to “1” during a power

on reset. The firmware can check bits 4 and 6 in the reset

handler to determine whether a reset was caused by a Power

On condition or a Watch Dog Timeout. PORS is used to

determine suspend start-up timer value of 128 µs or 96 ms.

The “USB Bus Reset” (bit 5) will occur when a USB bus reset

is received. The USB Bus Reset is a singled-ended zero (SE0)

that lasts more than 8 microseconds. An SE0 is defined as the

condition in which both the D+ line and the D– line are LOW

at the same time. When the SIE detects this condition, the

USB Bus Reset bit is set in the Processor Status and Control

note this is an interrupt to the microcontroller and does not

actually reset the processor.

The “Watch Dog Reset” (bit 6) is set during a reset initiated by

the Watch Dog Timer. This indicates the Watch Dog Timer

went for more than 8 ms between watch dog clears.

The “IRQ Pending” (bit 7) indicates one or more of the inter-

rupts has been recognized as active. The interrupt

acknowledge sequence should clear this bit until the next

interrupt is detected.

During Power-on Reset, the Processor Status and Control

(bit 4 set) has occurred and no interrupts are pending (bit 7

clear) yet.

During a Watch Dog Reset, the Processor Status and Control

Reset (bit 6 set) has occurred and no interrupts are pending

(bit 7 clear) yet.

Interrupts

All interrupts are maskable by the Global Interrupt Enable

Writing a “1” to a bit position enables the interrupt associated

with that bit position. During a reset, the contents the Global

Interrupt Enable Register and USB End Point Interrupt Enable

Pending interrupt requests are recognized during the last clock

cycle of the current instruction. When servicing an interrupt,

the hardware will first disable all interrupts by clearing the

Interrupt Enable bit in the Processor Status and Control

cleared. This is followed by a CALL instruction to the ROM

address associated with the interrupt being serviced (i.e., the

Interrupt Vector). The instruction in the interrupt table is

typically a JMP instruction to the address of the Interrupt

Service Routine (ISR). The user can re-enable interrupts in the

interrupt service routine by executing an EI instruction. Inter-

rupts can be nested to a level limited only by the available

stack space.

The Program Counter value as well as the Carry and Zero

flags (CF, ZF) are automatically stored onto the Program Stack

by the CALL instruction as part of the interrupt acknowledge

process. The user firmware is responsible for insuring that the

processor state is preserved and restored during an interrupt.

The PUSH A instruction should be used as the first command

in the ISR to save the accumulator value and the POP A

instruction should be used just before the RETI instruction to

restore the accumulator value. The program counter CF and

ZF are restored and interrupts are enabled when the RETI

instruction is executed.

Table 25.Global Interrupt Enable Register

Addr: 0x20 Global Interrupt Enable Register

76543210

Reserved Reserved GPIO

Interrupt

Enable

DAC

Interrupt

Enable

Reserved 1.024-ms

Interrupt

Enable

128-µsec

Interrupt

Enable

USB Bus RST

Interrupt

Enable

R/W R/W R/W R/W R/W

Table 26.USB End Point Interrupt Enable Register

Addr: 0x21 USB End Point Interrupt Enable Register

76543210

Reserved Reserved Reserved Reserved Reserved EPA2

Interrupt

Enable

EPA1

Interrupt

Enable

EPA0

Interrupt

Enable

R/W R/W R/W

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