Cypress CY7C68014A, CY7C68013, CY7C68015A WU2, FIFOADR0, IFCONFIG1..0, FIFOADR1, Pktend, Slcs#

									CY7C68013A, CY7C68014A
									CY7C68015A, CY7C68016A
Table 11. FX2LP Pin Descriptions (continued)
128		100	56	56	56 VF-	Name	Type	Default	Description
TQFP	TQFP		SSOP	QFN	BGA
85		70	43	36	7F	PA3 or	IO/Z	I	Multiplexed pin whose function is selected by:
						WU2		(PA3)	WAKEUP.7 and OEA.3
									PA3 is a bidirectional IO port pin.
									WU2 is an alternate source for USB Wakeup, enabled
									by WU2EN bit (WAKEUP.1) and polarity set by
									WU2POL (WAKEUP.4). If the 8051 is in suspend and
									WU2EN = 1, a transition on this pin starts up the oscil-
									lator and interrupts the 8051 to enable it to exit the
									suspend mode. Asserting this pin inhibits the chip from
									suspending, if WU2EN = 1.
89		71	44	37	6F	PA4 or	IO/Z	I	Multiplexed pin whose function is selected by:
						FIFOADR0		(PA4)	IFCONFIG[1..0].
									PA4 is a bidirectional IO port pin.
									FIFOADR0 is an input-only address select for the slave
									FIFOs connected to FD[7..0] or FD[15..0].
90		72	45	38	8C	PA5 or	IO/Z	I	Multiplexed pin whose function is selected by:
						FIFOADR1		(PA5)	IFCONFIG[1..0].
									PA5 is a bidirectional IO port pin.
									FIFOADR1 is an input-only address select for the slave
									FIFOs connected to FD[7..0] or FD[15..0].
91		73	46	39	7C	PA6 or	IO/Z	I	Multiplexed pin whose function is selected by the
						PKTEND		(PA6)	IFCONFIG[1:0] bits.
									PA6 is a bidirectional IO port pin.
									PKTEND is an input used to commit the FIFO packet
									data to the endpoint and whose polarity is program-
									mable via FIFOPINPOLAR.5.
92		74	47	40	6C	PA7 or	IO/Z	I	Multiplexed pin whose function is selected by the
						FLAGD or		(PA7)	IFCONFIG[1:0] and PORTACFG.7 bits.
						SLCS#			PA7 is a bidirectional IO port pin.
									FLAGD is a programmable slave-FIFO output status
									flag signal.
									SLCS# gates all other slave FIFO enable/strobes
Port	B
44		34	25	18	3H	PB0 or	IO/Z	I	Multiplexed pin whose function is selected by the
						FD[0]		(PB0)	following bits: IFCONFIG[1..0].
									PB0 is a bidirectional IO port pin.
									FD[0] is the bidirectional FIFO/GPIF data bus.
45		35	26	19	4F	PB1 or	IO/Z	I	Multiplexed pin whose function is selected by the
						FD[1]		(PB1)	following bits: IFCONFIG[1..0].
									PB1 is a bidirectional IO port pin.
									FD[1] is the bidirectional FIFO/GPIF data bus.
46		36	27	20	4H	PB2 or	IO/Z	I	Multiplexed pin whose function is selected by the
						FD[2]		(PB2)	following bits: IFCONFIG[1..0].
									PB2 is a bidirectional IO port pin.
									FD[2] is the bidirectional FIFO/GPIF data bus.
47		37	28	21	4G	PB3 or	IO/Z	I	Multiplexed pin whose function is selected by the
						FD[3]		(PB3)	following bits: IFCONFIG[1..0].
									PB3 is a bidirectional IO port pin.
									FD[3] is the bidirectional FIFO/GPIF data bus.
54		44	29	22	5H	PB4 or	IO/Z	I	Multiplexed pin whose function is selected by the
						FD[4]		(PB4)	following bits: IFCONFIG[1..0].
									PB4 is a bidirectional IO port pin.
									FD[4] is the bidirectional FIFO/GPIF data bus.
Document #: 38-08032 Rev. *L									Page 23 of 62

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