Register Addresses, External Code Memory, EA = | Cypress CY7C68015A

CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

Figure 4. External Code Memory, EA = 1

Inside FX2LP

Outside FX2LP

FFFF

7.5 KBytes

(OK to populate

USB regs and

4K FIFO buffers

data memory

(RD#,WR#)

here—RD#/WR#

E200

strobes are not

E1FF

active)

0.5 KBytes RAM

E000

Data (RD#,WR#)*

40 KBytes

External

64 KBytes

Data

Memory

External

(RD#,WR#)

Code

Memory

(PSEN#)

3FFF

16 KBytes

(Ok to populate

data memory

RAM

here—RD#/WR#

Data

strobes are not

(RD#,WR#)*

active)

0000

Data

Code

*SUDPTR, USB upload/download, I2C interface boot access

3.11 Register Addresses

FFFF

4 KBytes EP2-EP8

buffers

(8 x 512)

F000

EFFF

E800

2 KBytes RESERVED

E7FF

64 Bytes EP1IN

E7C0

E7BF

64 Bytes EP1OUT

E780

E77F

64 Bytes EP0 IN/OUT

E740

E73F

64 Bytes RESERVED

E700

E6FF

8051 Addressable Registers

E500

(512)

E4FF

Reserved (128)

E480

E47F

128 bytes GPIF Waveforms

E400

E3FF

Reserved (512)

E200

E1FF

512 bytes

E000

8051 xdata RAM

Document #: 38-08032 Rev. *L

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Cypress CY7C68015A, CY7C68013, CY7C68016A, CY7C68014A manual Register Addresses, External Code Memory, EA =

CY7C68016A, CY7C68014A, CY7C68015A, CY7C68013 specifications

The Cypress CY7C68013, CY7C68015A, CY7C68014A, and CY7C68016A are part of Cypress Semiconductor's EZ-USB family of microcontrollers, known for their high performance and flexibility in USB applications. These devices are primarily used for USB interfacing and have gained popularity in various industries due to their robust features and capabilities.

One of the main features of the CY7C68013 is its Dual FIFO architecture, allowing for efficient data transfer between USB and the system memory. This feature optimizes throughput and reduces CPU overhead, making it an excellent choice for applications that require high-speed data exchange, such as video streaming, data acquisition, and industrial automation. The device is equipped with a USB 2.0 interface which supports full-speed operation at 12 Mbps, ensuring compatibility with a wide range of USB devices.

The CY7C68015A, a similar variant, offers additional memory options, providing users with the flexibility to select the necessary capacity for their specific applications. This part is particularly useful in scenarios that demand more users or higher data storage, making it ideal for complex USB peripherals like printers and multifunction devices. Moreover, it includes a unique capability of upgradeable firmware, ensuring that the device remains relevant and functional as technology evolves.

In contrast, the CY7C68014A stands out with its support for isochronous data transfers, making it suitable for real-time applications that require timely data delivery. This is particularly important in audio and video applications where delays can impact performance. The device incorporates advanced power management features, allowing it to operate efficiently both in low and high-power modes.

Lastly, the CY7C68016A integrates enhanced security features, positioning it as an ideal choice for applications that require data integrity and protection against unauthorized access. It supports various encryption standards and provides secure boot capabilities, making it suitable for secure environments such as financial transactions and sensitive data processing.

In summary, the CY7C68013, CY7C68015A, CY7C68014A, and CY7C68016A microcontrollers offer a versatile suite of features that cater to a wide array of USB applications. Their design emphasizes performance, flexibility, and security, making them essential components in today's rapidly evolving technology landscape. Whether in consumer electronics, industrial automation, or specialized applications, these devices provide the reliability and efficiency that engineers and developers require.

Contents

Cypress Semiconductor Corporation 198 Champion Court Features CY7C68013A/14A/15A/16A Logic Block Diagram Features CY7C68013A/14A onlyFeatures CY7C68015A/16A only Functional Overview Applications Bus-powered Applications USB Boot MethodsReNumeration Interrupt System INT2 USB Interrupts Priority INT2VEC Value SourceFIFO/GPIF Interrupt INT4 Reset Pin Reset and Wakeup Program/Data RAM Reset Timing Values Condition Internal Code Memory, EA = Inside FX2LP Outside FX2LP External Code Memory, EA = Register Addresses Endpoint Configurations High -speed Mode Setup Data BufferEndpoint RAM Size × 64 bytes Endpoints 0 × 512 bytes Master/Slave Control Signals 12.5 Default Full-Speed Alternate SettingsExternal Fifo Interface Architecture ECC Generation7 Autopointer AccessGpif USB Uploads and Downloads Compatible with Previous Generation EZ-USB FX2 18 I2C ControllerPart Number Conversion Table Package Description 20 CY7C68013A/14A and CY7C68015A/16A Differences Pin AssignmentsIfclk PE0 PE1 128 Pin Tqfp CY7C68013A/CY7C68014A CY7C68013A/CY7C68014A CY7C68013A/CY7C68014A 56-pin Ssop Pin Assignment CY7C68013A/CY7C68014A 56-pin Ssop CY7C68015A/CY7C68016A Pin QFN CY7C68013A 56-pin Vfbga Pin Assignment Top View CY7C68013A/15A Pin Descriptions FX2LP Pin Descriptions 128 100 56 VF Name Type Default 56 VF Name Type Default Description FX2LP Pin DescriptionsPort WU2 IFCONFIG1..0FIFOADR0 FIFOADR1 PORTCCFG.0 GPIFADR0GPIFADR1 PORTCCFG.1 T0OUT Port ET1OUT T2OUT INT6 RXD1OUTT2EX GPIFADR8 Flagc FlagbCTL3 CTL4 Ground FX2LP Register Summary Register Summary Register can only be reset, it cannot be set Epie EP0CS E6CB Flowstb DPL0 = both read/write bit Absolute Maximum Ratings Thermal CharacteristicsOperating Conditions ΘJc + θCa DC Characteristics AC Electrical CharacteristicsUSB Transceiver Program Memory Read ClkoutProgram Memory Read Parameters Description Min Typ Max Unit Data Memory Read CLKOUT17Data Memory Read Parameters Description Min Typ Max Unit Data Memory Write Stretch =Data Memory Write Parameters Description Min Max Unit WR# Strobe Function when Portc is Accessed by Portc Strobe Feature Timings Gpif Synchronous Signals Timing Diagram20 Gpif Synchronous Signals Slave Fifo Synchronous Read Slave Fifo Synchronous Read Timing Diagram20 Slave Fifo Asynchronous Read Slave Fifo Asynchronous Read Timing Diagram20 Slave Fifo Synchronous Write Slave Fifo Synchronous Write Timing Diagram20 Slave Fifo Synchronous Packet End Strobe Slave Fifo Asynchronous Write Slave Fifo Asynchronous Packet End Strobe Slave Fifo Synchronous Write Sequence and Timing Diagram Slave Fifo Address to Flags/Data Slave Fifo Output Enable Slave Fifo Synchronous Address FIFOADR10 to SLRD/SLWR/PKTEND Setup TimeSlave Fifo Asynchronous Address RD/WR/PKTEND to FIFOADR10 Hold Time Single and Burst Synchronous Read Example Sequence Diagram 10.17.2 Single and Burst Synchronous Write Slave Fifo Asynchronous Read Sequence and Timing Diagram20 Sequence Diagram of a Single and Burst Asynchronous Read Slave Fifo Asynchronous Write Sequence and Timing Diagram20 Sequence Diagram of a Single and Burst Asynchronous Write Ideal for non-battery powered applications Ideal for battery powered applicationsOrdering Information Development Tool Kit Lead Shrunk Small Outline Package O56 Package Diagrams Lead QFN 8 x 8 mm LF56A Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A100RA Lead Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A128 Vfbga 5 x 5 x 1.0 mm 0.50 Pitch, 0.30 Ball BZ56 PCB Layout Recommendations Cross-section of the Area Underneath the QFN Package Quad Flat Package No Leads QFN Package Design Notes Issue Orig. Description of Change Date Pyrs Cmcc