Inside FX2LP Outside FX2LP | Cypress CY7C68013, CY7C68015A specs

CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

Figure 3. Internal Code Memory, EA = 0

Inside FX2LP

Outside FX2LP

FFFF

7.5 KBytes

(OK to populate

USB regs and

4K FIFO buffers

data memory

(RD#,WR#)

here—RD#/WR#

E200

strobes are not

E1FF

active)

0.5 KBytes RAM

E000

Data (RD#,WR#)*

48 KBytes

40 KBytes

External

Code

External

Memory

Data

(PSEN#)

Memory

(RD#,WR#)

3FFF

(Ok to populate

(OK to populate

16 KBytes RAM

data memory

program

Code and Data

here—RD#/WR#

memory here—

(PSEN#,RD#,WR#)*

strobes are not

PSEN# strobe

0000

active)

is not active)

Data

Code

*SUDPTR, USB upload/download, I2C interface boot access

Document #: 38-08032 Rev. *L

Page 8 of 62

[+] Feedback

Page 8

Image 8

Cypress CY7C68013, CY7C68015A, CY7C68016A, CY7C68014A manual Inside FX2LP Outside FX2LP, Internal Code Memory, EA =

CY7C68016A, CY7C68014A, CY7C68015A, CY7C68013 specifications

The Cypress CY7C68013, CY7C68015A, CY7C68014A, and CY7C68016A are part of Cypress Semiconductor's EZ-USB family of microcontrollers, known for their high performance and flexibility in USB applications. These devices are primarily used for USB interfacing and have gained popularity in various industries due to their robust features and capabilities.

One of the main features of the CY7C68013 is its Dual FIFO architecture, allowing for efficient data transfer between USB and the system memory. This feature optimizes throughput and reduces CPU overhead, making it an excellent choice for applications that require high-speed data exchange, such as video streaming, data acquisition, and industrial automation. The device is equipped with a USB 2.0 interface which supports full-speed operation at 12 Mbps, ensuring compatibility with a wide range of USB devices.

The CY7C68015A, a similar variant, offers additional memory options, providing users with the flexibility to select the necessary capacity for their specific applications. This part is particularly useful in scenarios that demand more users or higher data storage, making it ideal for complex USB peripherals like printers and multifunction devices. Moreover, it includes a unique capability of upgradeable firmware, ensuring that the device remains relevant and functional as technology evolves.

In contrast, the CY7C68014A stands out with its support for isochronous data transfers, making it suitable for real-time applications that require timely data delivery. This is particularly important in audio and video applications where delays can impact performance. The device incorporates advanced power management features, allowing it to operate efficiently both in low and high-power modes.

Lastly, the CY7C68016A integrates enhanced security features, positioning it as an ideal choice for applications that require data integrity and protection against unauthorized access. It supports various encryption standards and provides secure boot capabilities, making it suitable for secure environments such as financial transactions and sensitive data processing.

In summary, the CY7C68013, CY7C68015A, CY7C68014A, and CY7C68016A microcontrollers offer a versatile suite of features that cater to a wide array of USB applications. Their design emphasizes performance, flexibility, and security, making them essential components in today's rapidly evolving technology landscape. Whether in consumer electronics, industrial automation, or specialized applications, these devices provide the reliability and efficiency that engineers and developers require.

Contents

Features CY7C68013A/14A/15A/16A Cypress Semiconductor Corporation 198 Champion Court Features CY7C68015A/16A only Logic Block DiagramFeatures CY7C68013A/14A only Applications Functional Overview USB Boot Methods Bus-powered ApplicationsReNumeration Interrupt System FIFO/GPIF Interrupt INT4 INT2 USB InterruptsPriority INT2VEC Value Source Reset and Wakeup Reset Pin Reset Timing Values Condition Program/Data RAM Inside FX2LP Outside FX2LP Internal Code Memory, EA = Register Addresses External Code Memory, EA = Setup Data Buffer Endpoint Configurations High -speed ModeEndpoint RAM Size × 64 bytes Endpoints 0 × 512 bytes 12.5 Default Full-Speed Alternate Settings Master/Slave Control SignalsExternal Fifo Interface Architecture Autopointer Access ECC Generation7Gpif USB Uploads and Downloads 18 I2C Controller Compatible with Previous Generation EZ-USB FX2Part Number Conversion Table Package Description Pin Assignments 20 CY7C68013A/14A and CY7C68015A/16A DifferencesIfclk PE0 PE1 128 CY7C68013A/CY7C68014A Pin Tqfp CY7C68013A/CY7C68014A CY7C68013A/CY7C68014A 56-pin Ssop CY7C68013A/CY7C68014A 56-pin Ssop Pin Assignment CY7C68015A/CY7C68016A Pin QFN CY7C68013A 56-pin Vfbga Pin Assignment Top View FX2LP Pin Descriptions 128 100 56 VF Name Type Default CY7C68013A/15A Pin Descriptions Port 56 VF Name Type Default DescriptionFX2LP Pin Descriptions IFCONFIG1..0 WU2FIFOADR0 FIFOADR1 GPIFADR0 PORTCCFG.0GPIFADR1 PORTCCFG.1 Port E T0OUTT1OUT T2OUT RXD1OUT INT6T2EX GPIFADR8 Flagb FlagcCTL3 CTL4 Ground Register Summary FX2LP Register Summary Register can only be reset, it cannot be set Epie EP0CS E6CB Flowstb DPL0 = both read/write bit Thermal Characteristics Absolute Maximum RatingsOperating Conditions ΘJc + θCa USB Transceiver DC CharacteristicsAC Electrical Characteristics Program Memory Read Parameters Description Min Typ Max Unit Program Memory ReadClkout Data Memory Read Parameters Description Min Typ Max Unit Data Memory ReadCLKOUT17 Data Memory Write Parameters Description Min Max Unit Data Memory WriteStretch = Portc Strobe Feature Timings WR# Strobe Function when Portc is Accessed by Gpif Synchronous Signals Gpif Synchronous Signals Timing Diagram20 Slave Fifo Synchronous Read Timing Diagram20 Slave Fifo Synchronous Read Slave Fifo Asynchronous Read Timing Diagram20 Slave Fifo Asynchronous Read Slave Fifo Synchronous Write Timing Diagram20 Slave Fifo Synchronous Write Slave Fifo Asynchronous Write Slave Fifo Synchronous Packet End Strobe Slave Fifo Synchronous Write Sequence and Timing Diagram Slave Fifo Asynchronous Packet End Strobe Slave Fifo Output Enable Slave Fifo Address to Flags/Data FIFOADR10 to SLRD/SLWR/PKTEND Setup Time Slave Fifo Synchronous AddressSlave Fifo Asynchronous Address RD/WR/PKTEND to FIFOADR10 Hold Time Sequence Diagram Single and Burst Synchronous Read Example 10.17.2 Single and Burst Synchronous Write Sequence Diagram of a Single and Burst Asynchronous Read Slave Fifo Asynchronous Read Sequence and Timing Diagram20 Sequence Diagram of a Single and Burst Asynchronous Write Slave Fifo Asynchronous Write Sequence and Timing Diagram20 Ideal for battery powered applications Ideal for non-battery powered applicationsOrdering Information Development Tool Kit Package Diagrams Lead Shrunk Small Outline Package O56 Lead QFN 8 x 8 mm LF56A Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A100RA Lead Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A128 PCB Layout Recommendations Vfbga 5 x 5 x 1.0 mm 0.50 Pitch, 0.30 Ball BZ56 Quad Flat Package No Leads QFN Package Design Notes Cross-section of the Area Underneath the QFN Package Issue Orig. Description of Change Date Cmcc Pyrs

Cypress CY7C68013, CY7C68015A, CY7C68016A Inside FX2LP Outside FX2LP, Internal Code Memory, EA =

Models: CY7C68016A CY7C68014A CY7C68015A CY7C68013

Figure 3. Internal Code Memory, EA = 0

Inside FX2LP

Outside FX2LP

3FFF

CY7C68016A, CY7C68014A, CY7C68015A, CY7C68013 specifications