CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Document #: 38-08032 Rev. *L Page 39 of 62
10.3 Data Memory Read Figure 13. Data Memory Read Timing Diagram
data in
tCL
A[15..0]
tAV tAV
RD#
tSTBL tSTBH
tDH
D[7..0] data in
tACC1
[19] tDSU
Stretch = 0
Stretch = 1
tCL
A[15..0]
tAV
RD#
tDH
D[7..0] tACC1
tDSU
CS#
CS#
tSCSL
OE# tSOEL
CLKOUT[17]
CLKOUT[17]
[19]
Table 16. Data Memory Read Parameters
Parameter Description Min Typ Max Unit Notes
tCL 1/CLKOUT Frequency 20.83 ns 48 MHz
41.66 ns 24 MHz
83.2 ns 12 MHz
tAV Delay from Clock to Valid Address 10.7 ns
tSTBL Clock to RD LOW 11 ns
tSTBH Clock to RD HIGH 11 ns
tSCSL Clock to CS LOW 13 ns
tSOEL Clock to OE LOW 11.1 ns
tDSU Data Setup to Clock 9.6 ns
tDH Data Hold Time 0 ns
When using the AUTPOPTR1 or AUTOPTR2 to address external memory, the address of AUTOPTR1 is only active while either
RD# or WR# are active. The address of AUTOPTR2 is active throughout the cycle and meets the above address valid time for
which is based on the stretch value
Note
19.tACC2 and tACC3 are computed from the above parameters as follows:
tACC2(24 MHz) = 3*tCL – tAV –tDSU = 106 ns
tACC2(48 MHz) = 3*tCL – tAV – tDSU = 43 ns
tACC3(24 MHz) = 5*tCL – tAV –tDSU = 190 ns
tACC3(48 MHz) = 5*tCL – tAV – tDSU = 86 ns.
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