CY7C68013A, CY7C68014A

 

 

 

 

 

CY7C68015A, CY7C68016A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 4. Individual FIFO/GPIF Interrupt Sources

 

 

 

 

 

 

 

 

Priority

INT4VEC Value

Source

Notes

 

 

1

80

 

 

EP2PF

Endpoint 2 Programmable Flag

 

 

 

 

 

 

 

 

 

2

84

 

 

EP4PF

Endpoint 4 Programmable Flag

 

 

 

 

 

 

 

 

 

3

88

 

 

EP6PF

Endpoint 6 Programmable Flag

 

 

 

 

 

 

 

4

8C

EP8PF

Endpoint 8 Programmable Flag

 

 

 

 

 

 

 

 

 

5

90

 

 

EP2EF

Endpoint 2 Empty Flag

 

 

 

 

 

 

 

 

 

6

94

 

 

EP4EF

Endpoint 4 Empty Flag

 

 

 

 

 

 

 

 

 

7

98

 

 

EP6EF

Endpoint 6 Empty Flag

 

 

 

 

 

 

 

8

9C

EP8EF

Endpoint 8 Empty Flag

 

 

 

 

 

 

 

9

A0

EP2FF

Endpoint 2 Full Flag

 

 

 

 

 

 

 

10

A4

EP4FF

Endpoint 4 Full Flag

 

 

 

 

 

 

 

11

A8

EP6FF

Endpoint 6 Full Flag

 

 

 

 

 

 

 

12

AC

EP8FF

Endpoint 8 Full Flag

 

 

 

 

 

 

 

13

B0

GPIFDONE

GPIF Operation Complete

 

 

 

 

 

 

 

14

B4

GPIFWF

GPIF Waveform

 

 

 

 

 

 

 

 

 

 

If Autovectoring is enabled (AV4EN = 1 in the INTSET-UP register), the FX 2LP substitutes its INT4VEC byte. Therefore, if the high byte (“page”) of a jump-table address is preloaded at location 0x0054, the automatically inserted INT4VEC byte at 0x0055 directs the jump to the correct address out of the 14 addresses within the page. When the ISR occurs, the FX2LP pushes the program counter onto its stack then jumps to address 0x0053, where it expects to find a “jump” instruction to the ISR Interrupt service routine.

3.9 Reset and Wakeup

3.9.1 Reset Pin

The input pin, RESET#, resets the FX2LP when asserted. This pin has hysteresis and is active LOW. When a crystal is used with

the CY7C680xxA the reset period must allow for the stabilization of the crystal and the PLL. This reset period must be approxi- mately 5 ms after VCC reaches 3.0V. If the crystal input pin is driven by a clock signal the internal PLL stabilizes in 200 μs after VCC has reached 3.0V.[3]

Figure 2 on page 7 shows a power on reset condition and a reset applied during operation. A power on reset is defined as the time reset that is asserted while power is being applied to the circuit. A powered reset is when the FX2LP powered on and operating and the RESET# pin is asserted.

Cypress provides an application note which describes and recommends power on reset implementation. For more infor- mation about reset implementation for the FX2 family of products visit http://www.cypress.com.

Note

3. If the external clock is powered at the same time as the CY7C680xxA and has a stabilization wait period, it must be added to the 200 μs.

Document #: 38-08032 Rev. *L

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Cypress CY7C68016A, CY7C68013, CY7C68015A, CY7C68014A manual Reset and Wakeup, Reset Pin
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CY7C68016A, CY7C68014A, CY7C68015A, CY7C68013 specifications

The Cypress CY7C68013, CY7C68015A, CY7C68014A, and CY7C68016A are part of Cypress Semiconductor's EZ-USB family of microcontrollers, known for their high performance and flexibility in USB applications. These devices are primarily used for USB interfacing and have gained popularity in various industries due to their robust features and capabilities.

One of the main features of the CY7C68013 is its Dual FIFO architecture, allowing for efficient data transfer between USB and the system memory. This feature optimizes throughput and reduces CPU overhead, making it an excellent choice for applications that require high-speed data exchange, such as video streaming, data acquisition, and industrial automation. The device is equipped with a USB 2.0 interface which supports full-speed operation at 12 Mbps, ensuring compatibility with a wide range of USB devices.

The CY7C68015A, a similar variant, offers additional memory options, providing users with the flexibility to select the necessary capacity for their specific applications. This part is particularly useful in scenarios that demand more users or higher data storage, making it ideal for complex USB peripherals like printers and multifunction devices. Moreover, it includes a unique capability of upgradeable firmware, ensuring that the device remains relevant and functional as technology evolves.

In contrast, the CY7C68014A stands out with its support for isochronous data transfers, making it suitable for real-time applications that require timely data delivery. This is particularly important in audio and video applications where delays can impact performance. The device incorporates advanced power management features, allowing it to operate efficiently both in low and high-power modes.

Lastly, the CY7C68016A integrates enhanced security features, positioning it as an ideal choice for applications that require data integrity and protection against unauthorized access. It supports various encryption standards and provides secure boot capabilities, making it suitable for secure environments such as financial transactions and sensitive data processing.

In summary, the CY7C68013, CY7C68015A, CY7C68014A, and CY7C68016A microcontrollers offer a versatile suite of features that cater to a wide array of USB applications. Their design emphasizes performance, flexibility, and security, making them essential components in today's rapidly evolving technology landscape. Whether in consumer electronics, industrial automation, or specialized applications, these devices provide the reliability and efficiency that engineers and developers require.
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