CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Document #: 38-08032 Rev. *L Page 43 of 62
10.7 Slave FIFO Synchronous Read
Figure 18. Slave FIFO Synchronous Read Timing Diagram[20]
IFCLK
SLRD
FLAGS
SLOE
tSRD tRDH
tOEon tXFD
tXFLG
DATA
tIFCLK
N+1
tOEoff
N
Table 20. Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK[21]
Parameter Description Min Max Unit
tIFCLK IFCLK Period 20.83 ns
tSRD SLRD to Clock Setup Time 18.7 ns
tRDH Clock to SLRD Hold Time 0 ns
tOEon SLOE Turn-on to FIFO Data Valid 10.5 ns
tOEoff SLOE Turn-off to FIFO Data Hold 10.5 ns
tXFLG Clock to FLAGS Output Propagation Delay 9.5 ns
tXFD Clock to FIFO Data Output Propagation Delay 11 ns
Table 21. Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK[21]
Parameter Description Min. Max. Unit
tIFCLK IFCLK Period 20.83 200 ns
tSRD SLRD to Clock Setup Time 12.7 ns
tRDH Clock to SLRD Hold Time 3.7 ns
tOEon SLOE Turn-on to FIFO Data Valid 10.5 ns
tOEoff SLOE Turn-off to FIFO Data Hold 10.5 ns
tXFLG Clock to FLAGS Output Propagation Delay 13.5 ns
tXFD Clock to FIFO Data Output Propagation Delay 15 ns
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