CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Document #: 38-08032 Rev. *L Page 46 of 62
10.10 Slave FIFO Asynchronous Write
Figure 21. Slave FIFO Asynchronous Write Timing Diagram[20]
10.11 Slave FIFO Synchronous Packet End Strobe
Figure 22. Slave FIFO Synchronous Packet End Strobe Timing Diagram[20]
DATA
tSFD tFDH
FLAGS tXFD
SLWR/SLCS#
tWRpwh
tWRpwl
SLWR
Table 25. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK [23]
Parameter Description Min Max Unit
tWRpwl SLWR Pulse LOW 50 ns
tWRpwh SLWR Pulse HIGH 70 ns
tSFD SLWR to FIFO DATA Setup Time 10 ns
tFDH FIFO DATA to SLWR Hold Time 10 ns
tXFD SLWR to FLAGS Output Propagation Delay 70 ns
FLAGS
tXFLG
IFCLK
PKTEND tSPE
tPEH
Table 26. Slave FIFO Synchronous Packet End Strobe Parameters with Internally Sourced IFCLK[21]
Parameter Description Min Max Unit
tIFCLK IFCLK Period 20.83 ns
tSPE PKTEND to Clock Setup Time 14.6 ns
tPEH Clock to PKTEND Hold Time 0 ns
tXFLG Clock to FLAGS Output Propagation Delay 9.5 ns
Table 27. Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK[21]
Parameter Description Min Max Unit
tIFCLK IFCLK Period 20.83 200 ns
tSPE PKTEND to Clock Setup Time 8.6 ns
tPEH Clock to PKTEND Hold Time 2.5 ns
tXFLG Clock to FLAGS Output Propagation Delay 13.5 ns
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