Cypress CY7C68015A, CY7C68013, CY7C68016A, CY7C68014A specs

CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

10.17.4 Sequence Diagram of a Single and Burst Asynchronous Write

Figure 34. Slave FIFO Asynchronous Write Sequence and Timing Diagram[20]

tSFA

tFAH

tSFA

tFAH

FIFOADR

t=0

tWRpwl

tWRpwh

T=0

tWRpwl

tWRpwh

tWRpwl

tWRpwh

tWRpwl

tWRpwh

SLWR

t =1

t=3

T=1

T=3

T=4

T=6

T=7

T=9

SLCS

tXFLG

FLAGS

tSFD

tFDH

FDH

SFD

FDH

SFD

DATA

N+1

N+2

N+3

t=2

T=2

T=5

T=8

tPEpwl

tPEpwh

PKTEND

Figure 34 shows the timing relationship of the SLAVE FIFO write in an asynchronous mode. The diagram shows a single write followed by a burst write of 3 bytes and committing the 4 byte short packet using PKTEND.

■At t = 0 the FIFO address is applied, insuring that it meets the setup time of tSFA. If SLCS is used, it must also be asserted (SLCS may be tied low in some applications).

■At t = 1 SLWR is asserted. SLWR must meet the minimum active pulse of tWRpwl and minimum de-active pulse width of tWRpwh. If the SLCS is used, it must be asserted with SLWR or before SLWR is asserted.

■At t = 2, data must be present on the bus tSFD before the deasserting edge of SLWR.

■At t = 3, deasserting SLWR causes the data to be written from the data bus to the FIFO and then increments the FIFO pointer.

The FIFO flag is also updated after tXFLG from the deasserting edge of SLWR.

The same sequence of events are shown for a burst write and is indicated by the timing marks of T = 0 through 5.

Note In the burst write mode, after SLWR is deasserted, the data is written to the FIFO and then the FIFO pointer is incremented to the next byte in the FIFO. The FIFO pointer is post incre- mented.

In Figure 34 after the four bytes are written to the FIFO and SLWR is deasserted, the short 4 byte packet can be committed to the host using the PKTEND. The external device should be designed to not assert SLWR and the PKTEND signal at the same time. It should be designed to assert the PKTEND after SLWR is deasserted and met the minimum deasserted pulse width. The FIFOADDR lines have to held constant during the PKTEND assertion.

Document #: 38-08032 Rev. *L

Page 53 of 62

[+] Feedback

CY7C68016A, CY7C68014A, CY7C68015A, CY7C68013 specifications

The Cypress CY7C68013, CY7C68015A, CY7C68014A, and CY7C68016A are part of Cypress Semiconductor's EZ-USB family of microcontrollers, known for their high performance and flexibility in USB applications. These devices are primarily used for USB interfacing and have gained popularity in various industries due to their robust features and capabilities.

One of the main features of the CY7C68013 is its Dual FIFO architecture, allowing for efficient data transfer between USB and the system memory. This feature optimizes throughput and reduces CPU overhead, making it an excellent choice for applications that require high-speed data exchange, such as video streaming, data acquisition, and industrial automation. The device is equipped with a USB 2.0 interface which supports full-speed operation at 12 Mbps, ensuring compatibility with a wide range of USB devices.

The CY7C68015A, a similar variant, offers additional memory options, providing users with the flexibility to select the necessary capacity for their specific applications. This part is particularly useful in scenarios that demand more users or higher data storage, making it ideal for complex USB peripherals like printers and multifunction devices. Moreover, it includes a unique capability of upgradeable firmware, ensuring that the device remains relevant and functional as technology evolves.

In contrast, the CY7C68014A stands out with its support for isochronous data transfers, making it suitable for real-time applications that require timely data delivery. This is particularly important in audio and video applications where delays can impact performance. The device incorporates advanced power management features, allowing it to operate efficiently both in low and high-power modes.

Lastly, the CY7C68016A integrates enhanced security features, positioning it as an ideal choice for applications that require data integrity and protection against unauthorized access. It supports various encryption standards and provides secure boot capabilities, making it suitable for secure environments such as financial transactions and sensitive data processing.

In summary, the CY7C68013, CY7C68015A, CY7C68014A, and CY7C68016A microcontrollers offer a versatile suite of features that cater to a wide array of USB applications. Their design emphasizes performance, flexibility, and security, making them essential components in today's rapidly evolving technology landscape. Whether in consumer electronics, industrial automation, or specialized applications, these devices provide the reliability and efficiency that engineers and developers require.

Cypress CY7C68015A, CY7C68013 manual Sequence Diagram of a Single and Burst Asynchronous Write

Models: CY7C68016A CY7C68014A CY7C68015A CY7C68013

10.17.4 Sequence Diagram of a Single and Burst Asynchronous Write

Figure 34. Slave FIFO Asynchronous Write Sequence and Timing Diagram[20]

Figure 34 shows the timing relationship of the SLAVE FIFO write in an asynchronous mode. The diagram shows a single write followed by a burst write of 3 bytes and committing the 4 byte short packet using PKTEND.

■At t = 0 the FIFO address is applied, insuring that it meets the setup time of tSFA. If SLCS is used, it must also be asserted (SLCS may be tied low in some applications).

■At t = 1 SLWR is asserted. SLWR must meet the minimum active pulse of tWRpwl and minimum de-active pulse width of tWRpwh. If the SLCS is used, it must be asserted with SLWR or before SLWR is asserted.

■At t = 2, data must be present on the bus tSFD before the deasserting edge of SLWR.

CY7C68016A, CY7C68014A, CY7C68015A, CY7C68013 specifications