Cypress CY7C68013, CY7C68014A, CY7C68015A, CY7C68016A 5. Register Summary

CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Document #: 38-08032 Rev. *L Page 29 of 62
5. Register Summary
FX2LP register bit definitions are described in the FX2LP TRM in greater detail.
Table 12. FX2LP Register Summary
Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access
GPIF Waveform Memories
E400 128 WAVEDATA GPIF Waveform
Descriptor 0, 1, 2, 3 data D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxxRW
E480 128 reserved
GENERAL CONFIGURATION
E50D GPCR2 General Purpose Configu-
ration Register 2 reserved reserved reserved FULL_SPEE D_ONLY reserved reserved reserved reserved 00000000R
E600 1CPUCS CPU Control & Status 0 0 PORTCSTB CLKSPD1 CLKSPD0 CLKINV CLKOE 8051RES 00000010rrbb bbbr
E601 1IFCONFIG Interface Configuration
(Ports, GPIF, slave FIFOs)IFCLKSRC 3048MHZ IFCLKOE IFCLKPOL ASYNC GSTATE IFCFG1 IFCFG0 10000000 RW
E602 1PINFLAGSAB[11]
Slave FIFO FLAGA and FLAGB Pin ConfigurationFLAGB3 FLAGB2 FLAGB1 FLAGB0 FLAGA3 FLAGA2 FLAGA1 FLAGA0 00000000RW
E603 1PINFLAGSCD[11] Slave FIFO FLAGC and
FLAGD Pin Configuration FLAGD3 FLAGD2 FLAGD1 FLAGD0 FLAGC3 FLAGC2 FLAGC1 FLAGC0 00000000RW
E604 1FIFORESET[11]
Restore FIFOS to default state NAKALL 0 0 0 EP3 EP2 EP1 EP0 xxxxxxxx W
E605 1BREAKPT Breakpoint Control 0 0 0 0 BREAK BPPULSE BPEN 000000000rrrrbbbr
E606 1BPADDRH Breakpoint Address H A15 A14 A13 A12 A11 A10 A9 A8 xxxxxxxx RW
E607 1BPADDRL Breakpoint Address L A7 A6 A5 A4 A3 A2 A1 A0 xxxxxxxx RW
E608 1UART230 230 Kbaud internally
generated ref. clock 0 0 0 0 0 0 230UART1 230UART0 00000000 rrrrrrbb
E609 1FIFOPINPOLAR[11]
Slave FIFO Interface pins polarity 0 0 PKTEND SLOE SLRD SLWR EF FF 00000000rrbbbbbb
E60A 1REVID Chip Revision rv7 rv6 rv5 rv4 rv3 rv2 rv1 rv0 RevA
00000001R
E60B 1REVCTL[11] Chip Revision Control 0 0 0 0 0 0 dyn_out enh_pkt 00000000rrr rrrbb
UDMA
E60C1GPIFHOLDAMOUNT MSTB Hold Time
(for UDMA) 0 0 0 0 0 0 HOLDTIME1HOLDTIME0 00 000000 rrrrrrbb
3reserved
ENDPOINT CONFIGURATION
E610 1EP1OUTCFG Endpoint 1-OUT
Configuration VALID 0TYPE1 TYPE0 0 0 0 0 10100000 brbbrrrr
E611 1EP1INCFG Endpoint 1-IN
Configuration VALID 0TYPE1 TYPE0 0 0 0 0 10100000 brbbrrrr
E612 1EP2CFG Endpoint 2 Configuration VALID DIR TYPE1 TYPE0 SIZE 0BUF1 BUF0 10100010 bbbbbrbb
E613 1EP4CFG Endpoint 4 Configuration VALID DIR TYPE1 TYPE0 0 0 0 0 10100000 bbbbrrrr
E614 1EP6CFG Endpoint 6 Configuration VALID DIR TYPE1 TYPE0 SIZE 0BUF1 BUF0 1110 0010 bbbbbrbb
E615 1EP8CFG Endpoint 8 Configuration VALID DIR TYPE1 TYPE0 0 0 0 0 11100 000 bbbbrrrr
2reserved
E618 1EP2FIFOCFG[11]
Endpoint 2 / slave FIFO configuration 0INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN0WORDWIDE 00000101 rbbbbbrb
E619 1EP4FIFOCFG[11]
Endpoint 4 / slave FIFO configuration 0INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN0WORDWIDE 00000101 rbbbbbrb
E61A 1EP6FIFOCFG[11]
Endpoint 6 / slave FIFO configuration 0INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN0WORDWIDE 00000101 rbbbbbrb
E61B 1EP8FIFOCFG[11]
Endpoint 8 / slave FIFO configuration 0INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN0WORDWIDE 00000101 rbbbbbrb
E61C4rese rved
E620 1EP2AUTOINLENH[11 Endpoint 2 AUTOIN
Packet Length H 0 0 0 0 0 PL10 PL9 PL8 00000010rrrrrbbb
E621 1EP2AUTOINLENL[11]Endpoint 2 AUTOIN
Packet Length L PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 000000 00 RW
E622 1EP4AUTOINLENH[11]Endpoint 4 AUTOIN
Packet Length H 0 0 0 0 0 0 PL9 PL8 00000010rrrrrrbb
E623 1EP4AUTOINLENL[11]Endpoint 4 AUTOIN
Packet Length L PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 000000 00 RW
E624 1EP6AUTOINLENH[11]Endpoint 6 AUTOIN
Packet Length H 0 0 0 0 0 PL10 PL9 PL8 00000010rrrrrbbb
E625 1EP6AUTOINLENL[11]Endpoint 6 AUTOIN
Packet Length L PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 000000 00 RW
E626 1EP8AUTOINLENH[11]Endpoint 8 AUTOIN
Packet Length H 0 0 0 0 0 0 PL9 PL8 00000010rrrrrrbb
E627 1EP8AUTOINLENL[11]Endpoint 8 AUTOIN
Packet Length L PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 000000 00 RW
E628 1ECCCFG ECC Configuration 0 0 0 0 0 0 0 ECCM 00000000rrrrrrrb
E629 1ECCRESET ECC Reset x x x x x x x x 00000000 W
E62A 1ECC1B0 ECC1 Byte 0 Address LINE15 LINE14 LINE13 LINE12 LINE11 LINE10 LINE9 LINE8 00000000 R
Note
11.Read and writes to these registers may require synchronization delay, see Technical Reference Manual for “Synchronization Delay.”
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