CY8C20x36/46/66, CY8C20396
Block Diagram
| Port 4 | Port 3 |
| Port 2 | Port 1 |
| Port 0 | 1.8/2.5/3V | PWRSYS | ||||
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PSoC CORE |
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SYSTEM BUS |
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| Global | Analog | Interconnect |
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1K/2K | Supervisory ROM (SROM) | 8K/16K/32K Flash |
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SRAM | Nonvolatile Memory |
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Interrupt |
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| Sleep | and | |
Controller |
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| Watchdog | |||||
6/12/24 | MHz Internal | Main Oscillator |
| Internal | Low | Speed | Oscillator | (ILO) | |||||
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| Multiple Clock Sources |
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CAPSENSE |
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| Analog |
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SYSTEM |
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| Reference |
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| CapSense |
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| Two |
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| Module |
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| Analog |
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| Comparators |
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| Mux |
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SYSTEM BUS
| I2C | Internal | System | POR | SPI | Three | Digital | |
USB | Voltage | and | Master/ | |||||
Slave | Resets | Programmable | Clocks | |||||
| References | LVD | Slave | |||||
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| Timers |
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| SYSTEM RESOURCES |
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Document Number: | Page 2 of 34 |
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